ddr_cntl_a_cal_top.v

来自「arm控制FPGA的DDR测试代码」· Verilog 代码 · 共 52 行

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_cal_top.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: It contains the instantiations for cal_ctl and tap_dly
///////////////////////////////////////////////////////////////////////////////


`timescale 1ns/100ps
module ddr_cntl_a_cal_top(clk0,
               clk0dcmlock,
               reset,
               tapForDqs_rl,
               tapForDqs_tb);


   input clk0;
   input clk0dcmlock;
   input reset;

 output [4:0]      tapForDqs_rl;
  output [4:0]      tapForDqs_tb;
   

   wire [31:0] flop2_val;
   reg  fpga_rst;


   always@(posedge clk0)begin
      fpga_rst <= ~(reset && clk0dcmlock);
   end


   ddr_cntl_a_cal_ctl_0 cal_ctl0 (.clk(clk0), .reset(fpga_rst), .flop2(flop2_val), .tapForDqs_tb(tapForDqs_tb),
					.tapForDqs_rl(tapForDqs_rl));
   ddr_cntl_a_tap_dly_0 tap_dly0 (.clk(clk0), .reset(fpga_rst), .tapIn(clk0), .flop2(flop2_val));

endmodule