ddr_cntl_a.pcf

arm控制FPGA的DDR测试代码

        LOCATE = SITE "SLICE_X2Y134" LEVEL 1;
COMP "main_00/top0/data_path0/dqs2_delayed_col0" LOCATE = SITE "SLICE_X2Y135"
        LEVEL 1;
COMP "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/delay1"
        LOCATE = SITE "SLICE_X2Y146" LEVEL 1;
COMP "main_00/top0/data_path0/dqs3_delayed_col0" LOCATE = SITE "SLICE_X2Y147"
        LEVEL 1;
COMP
        "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_en_inst/din_delay_1"
        LOCATE = SITE "SLICE_X3Y101" LEVEL 1;
COMP "main_00/top0/data_path0/fifo_11_wr_addr<1>" LOCATE = SITE "SLICE_X3Y112"
        LEVEL 1;
COMP "main_00/top0/data_path0/fifo_11_wr_addr<3>" LOCATE = SITE "SLICE_X3Y113"
        LEVEL 1;
COMP "main_00/top0/data_path0/fifo_21_wr_addr<1>" LOCATE = SITE "SLICE_X3Y130"
        LEVEL 1;
COMP "main_00/top0/data_path0/fifo_21_wr_addr<3>" LOCATE = SITE "SLICE_X3Y131"
        LEVEL 1;
COMP
        "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_en_inst/din_delay_1"
        LOCATE = SITE "SLICE_X3Y115" LEVEL 1;
COMP
        "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_en_inst/din_delay_1"
        LOCATE = SITE "SLICE_X3Y133" LEVEL 1;
COMP "main_00/top0/data_path0/fifo_31_wr_addr<1>" LOCATE = SITE "SLICE_X3Y142"
        LEVEL 1;
COMP "main_00/top0/data_path0/fifo_31_wr_addr<3>" LOCATE = SITE "SLICE_X3Y143"
        LEVEL 1;
COMP
        "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_en_inst/din_delay_1"
        LOCATE = SITE "SLICE_X3Y145" LEVEL 1;
COMP "cntrl0_DDR_DQ<16>" LOCATE = SITE "AA9" LEVEL 1;
COMP "cntrl0_DDR_DQ<24>" LOCATE = SITE "Y3" LEVEL 1;
COMP "cntrl0_DDR_A<0>" LOCATE = SITE "T7" LEVEL 1;
COMP "cntrl0_DDR_A<1>" LOCATE = SITE "T10" LEVEL 1;
COMP "cntrl0_DDR_DQ<6>" LOCATE = SITE "AD3" LEVEL 1;
COMP "cntrl0_DDR_A<2>" LOCATE = SITE "T9" LEVEL 1;
COMP "cntrl0_DDR_A<3>" LOCATE = SITE "U3" LEVEL 1;
COMP "cntrl0_DDR_A<4>" LOCATE = SITE "U2" LEVEL 1;
COMP "cntrl0_DDR_A<5>" LOCATE = SITE "U7" LEVEL 1;
COMP "cntrl0_DDR_A<6>" LOCATE = SITE "U6" LEVEL 1;
COMP "cntrl0_DDR_A<7>" LOCATE = SITE "V2" LEVEL 1;
COMP "cntrl0_DDR_A<8>" LOCATE = SITE "V1" LEVEL 1;
COMP "cntrl0_DDR_A<9>" LOCATE = SITE "V5" LEVEL 1;
COMP "cntrl0_DDR_DQS<1>" LOCATE = SITE "AC3" LEVEL 1;
COMP "cntrl0_DDR_DQ<29>" LOCATE = SITE "W4" LEVEL 1;
COMP "cntrl0_DDR_A<10>" LOCATE = SITE "V4" LEVEL 1;
COMP "cntrl0_DDR_A<11>" LOCATE = SITE "W5" LEVEL 1;
COMP "cntrl0_DDR_A<12>" LOCATE = SITE "V6" LEVEL 1;
COMP "cntrl0_DDR_DQ<5>" LOCATE = SITE "AE3" LEVEL 1;
COMP "cntrl0_rst_dqs_div_out" LOCATE = SITE "N9" LEVEL 1;
COMP "SYS_CLK" LOCATE = SITE "A15" LEVEL 1;
COMP "cntrl0_DDR_DQ<10>" LOCATE = SITE "AC7" LEVEL 1;
COMP "cntrl0_DDR_BA<0>" LOCATE = SITE "T5" LEVEL 1;
COMP "cntrl0_DDR_BA<1>" LOCATE = SITE "T8" LEVEL 1;
COMP "cntrl0_rst_dqs_div_in" LOCATE = SITE "N8" LEVEL 1;
COMP "cntrl0_DDR_DQ<15>" LOCATE = SITE "AB5" LEVEL 1;
COMP "cntrl0_DDR_DQ<23>" LOCATE = SITE "Y6" LEVEL 1;
COMP "cntrl0_DDR_DQ<31>" LOCATE = SITE "W2" LEVEL 1;
COMP "cntrl0_DDR_DQ<4>" LOCATE = SITE "AE2" LEVEL 1;
COMP "cntrl0_DDR_CS_N" LOCATE = SITE "T3" LEVEL 1;
COMP "cntrl0_DDR_DQS<0>" LOCATE = SITE "AE5" LEVEL 1;
COMP "cntrl0_DDR_DQ<28>" LOCATE = SITE "W3" LEVEL 1;
COMP "cntrl0_DDR_DQ<3>" LOCATE = SITE "AF2" LEVEL 1;
COMP "cntrl0_DDR_WE_N" LOCATE = SITE "T2" LEVEL 1;
COMP "SYS_CLKb" LOCATE = SITE "B15" LEVEL 1;
COMP "cntrl0_DDR_CAS_N" LOCATE = SITE "U9" LEVEL 1;
COMP "cntrl0_DDR_DQ<14>" LOCATE = SITE "AB4" LEVEL 1;
COMP "cntrl0_DDR_DQ<22>" LOCATE = SITE "Y5" LEVEL 1;
COMP "cntrl0_DDR_DQ<30>" LOCATE = SITE "W1" LEVEL 1;
COMP "cntrl0_DDR_DQ<2>" LOCATE = SITE "AG1" LEVEL 1;
COMP "cntrl0_DDR_DQ<19>" LOCATE = SITE "AA7" LEVEL 1;
COMP "cntrl0_DDR_DQ<27>" LOCATE = SITE "W9" LEVEL 1;
COMP "cntrl0_DDR_DQ<1>" LOCATE = SITE "AG4" LEVEL 1;
COMP "cntrl0_DDR_CKE" LOCATE = SITE "T6" LEVEL 1;
COMP "cntrl0_DDR_DQ<13>" LOCATE = SITE "AC2" LEVEL 1;
COMP "cntrl0_DDR_DQ<21>" LOCATE = SITE "Y8" LEVEL 1;
COMP "cntrl0_DDR_DQ<0>" LOCATE = SITE "AG3" LEVEL 1;
COMP "cntrl0_DDR_DQ<18>" LOCATE = SITE "AA2" LEVEL 1;
COMP "cntrl0_DDR_DQ<26>" LOCATE = SITE "Y1" LEVEL 1;
COMP "cntrl0_DDR_RAS_N" LOCATE = SITE "T4" LEVEL 1;
COMP "cntrl0_DDR_DQS<3>" LOCATE = SITE "W6" LEVEL 1;
COMP "cntrl0_DDR_DM<0>" LOCATE = SITE "AF1" LEVEL 1;
COMP "cntrl0_DDR_DM<1>" LOCATE = SITE "AC5" LEVEL 1;
COMP "cntrl0_DDR_DM<2>" LOCATE = SITE "AA3" LEVEL 1;
COMP "cntrl0_DDR_DM<3>" LOCATE = SITE "W8" LEVEL 1;
COMP "reset_in" LOCATE = SITE "R24" LEVEL 1;
COMP "cntrl0_DDR_DQ<9>" LOCATE = SITE "AD2" LEVEL 1;
COMP "cntrl0_DDR_DQ<12>" LOCATE = SITE "AB6" LEVEL 1;
COMP "cntrl0_DDR_DQ<20>" LOCATE = SITE "Y7" LEVEL 1;
COMP "cntrl0_DDR_DQ<17>" LOCATE = SITE "AB8" LEVEL 1;
COMP "cntrl0_DDR_DQ<25>" LOCATE = SITE "Y4" LEVEL 1;
COMP "cntrl0_DDR_DQ<8>" LOCATE = SITE "AD1" LEVEL 1;
COMP "cntrl0_DDR_DQS<2>" LOCATE = SITE "Y10" LEVEL 1;
COMP "cntrl0_led_error_output1" LOCATE = SITE "AA22" LEVEL 1;
COMP "cntrl0_DDR_DQ<7>" LOCATE = SITE "AD4" LEVEL 1;
COMP "cntrl0_DDR_CK<0>" LOCATE = SITE "V10" LEVEL 1;
COMP "cntrl0_DDR_CK<1>" LOCATE = SITE "V8" LEVEL 1;
COMP "cntrl0_DDR_DQ<11>" LOCATE = SITE "AC6" LEVEL 1;
COMP "cntrl0_DDR_CK_N<0>" LOCATE = SITE "W10" LEVEL 1;
COMP "cntrl0_DDR_CK_N<1>" LOCATE = SITE "V9" LEVEL 1;
PIN main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/U2/FF0_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/U2/FF0" PINNAME CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/U2/FF1_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/U2/FF1" PINNAME CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/U2/FF0_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/U2/FF0" PINNAME CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/U2/FF1_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/U2/FF1" PINNAME CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/U2/FF0_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/U2/FF0" PINNAME CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/U2/FF1_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/U2/FF1" PINNAME CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/U2/FF0_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/U2/FF0" PINNAME CK;
PIN main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/U2/FF1_pins<0> = BEL
        "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/U2/FF1" PINNAME CK;
PIN main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0_INST/FF0_pins<0> = BEL
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0_INST/FF0" PINNAME CK;
PIN main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0_INST/FF1_pins<0> = BEL
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0_INST/FF1" PINNAME CK;
PIN main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0B_INST/FF0_pins<0> = BEL
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0B_INST/FF0" PINNAME
        CK;
PIN main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0B_INST/FF1_pins<0> = BEL
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK0B_INST/FF1" PINNAME
        CK;
PIN main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1_INST/FF0_pins<0> = BEL
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1_INST/FF0" PINNAME CK;
PIN main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1_INST/FF1_pins<0> = BEL
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1_INST/FF1" PINNAME CK;
PIN main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1B_INST/FF0_pins<0> = BEL
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1B_INST/FF0" PINNAME
        CK;
PIN main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1B_INST/FF1_pins<0> = BEL
        "main_00/top0/iobs0/infrastructure_iobs0/DDRCLK1B_INST/FF1" PINNAME
        CK;
TIMEGRP infrastructure_top0_clk_dcm0_clk0dcm = BEL
        "infrastructure_top0/wait_200us" BEL "infrastructure_top0/sys_rst_o"
        BEL "infrastructure_top0/sys_rst180_o" BEL
        "infrastructure_top0/sys_rst_1" BEL "infrastructure_top0/sys_rst180_1"
        BEL "infrastructure_top0/sys_rst" BEL "infrastructure_top0/sys_rst180"
        BEL "infrastructure_top0/Counter200_0" BEL
        "infrastructure_top0/Counter200_1" BEL
        "infrastructure_top0/Counter200_2" BEL
        "infrastructure_top0/Counter200_3" BEL
        "infrastructure_top0/Counter200_4" BEL
        "infrastructure_top0/Counter200_5" BEL
        "infrastructure_top0/Counter200_6" BEL
        "infrastructure_top0/Counter200_7" BEL
        "infrastructure_top0/Counter200_8" BEL
        "infrastructure_top0/Counter200_9" BEL
        "infrastructure_top0/Counter200_10" BEL
        "infrastructure_top0/Counter200_11" BEL
        "infrastructure_top0/Counter200_12" BEL
        "infrastructure_top0/Counter200_13" BEL
        "infrastructure_top0/Counter200_14" BEL
        "infrastructure_top0/Counter200_15" BEL
        "infrastructure_top0/cal_top0/fpga_rst" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/enb_trans_two_dtct" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/trans_oneDtct" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/trans_twoDtct" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_0" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_1" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_2" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_3" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_4" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_5" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_6" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_7" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_8" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_9" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_10" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_11" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_12" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_13" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_14" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_15" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_16" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_17" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_18" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_19" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_20" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_21" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_22" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_23" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_24" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_25" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_26" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_27" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_28" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_29" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_30" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tap_dly_reg_31" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tapForDqs_rl_2" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tapForDqs_rl_1" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/tapForDqs_rl_3" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt1_0" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt1_1" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt1_2" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt1_3" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt1_4" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt1_5" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt_0" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt_1" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt_2" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt_3" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt_4" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt_5" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/phase_cnt_0" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/phase_cnt_1" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/phase_cnt_2" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/phase_cnt_3" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/phase_cnt_4" BEL
        "infrastructure_top0/cal_top0/cal_ctl0/cnt_0_1" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r0" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r1" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r2" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r3" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r4" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r5" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r6" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r7" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r8" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r9" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r10" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r11" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r12" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r13" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r14" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r15" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r16" BEL
        "infrastructure_top0/cal_top0/tap_dly0/r17" BEL