ddr_cntl_a.syr

arm控制FPGA的DDR测试代码

Synthesizing Unit <ddr_cntl_a_controller_iobs_0>.
    Related source file is "ddr_cntl_a_controller_iobs_0.v".
Unit <ddr_cntl_a_controller_iobs_0> synthesized.


Synthesizing Unit <ddr_cntl_a_infrastructure_iobs_0>.
    Related source file is "ddr_cntl_a_infrastructure_iobs_0.v".
WARNING:Xst:647 - Input <clk90> is never used.
Unit <ddr_cntl_a_infrastructure_iobs_0> synthesized.


Synthesizing Unit <ddr_cntl_a_wr_gray_cntr>.
    Related source file is "ddr_cntl_a_wr_gray_cntr.v".
    Found 16x4-bit ROM for signal <d_in>.
    Summary:
	inferred   1 ROM(s).
Unit <ddr_cntl_a_wr_gray_cntr> synthesized.


Synthesizing Unit <ddr_cntl_a_fifo_1_wr_en_0>.
    Related source file is "ddr_cntl_a_fifo_1_wr_en_0.v".
WARNING:Xst:1780 - Signal <din_delay> is never used or assigned.
Unit <ddr_cntl_a_fifo_1_wr_en_0> synthesized.


Synthesizing Unit <ddr_cntl_a_fifo_0_wr_en_0>.
    Related source file is "ddr_cntl_a_fifo_0_wr_en_0.v".
Unit <ddr_cntl_a_fifo_0_wr_en_0> synthesized.


Synthesizing Unit <ddr_cntl_a_dqs_delay>.
    Related source file is "ddr_cntl_a_dqs_delay.v".
Unit <ddr_cntl_a_dqs_delay> synthesized.


Synthesizing Unit <ddr_cntl_a_RAM8D_0>.
    Related source file is "ddr_cntl_a_RAM8D_0.v".
Unit <ddr_cntl_a_RAM8D_0> synthesized.


Synthesizing Unit <ddr_cntl_a_rd_gray_cntr>.
    Related source file is "ddr_cntl_a_rd_gray_cntr.v".
    Found 16x4-bit ROM for signal <d_in>.
    Summary:
	inferred   1 ROM(s).
Unit <ddr_cntl_a_rd_gray_cntr> synthesized.


Synthesizing Unit <ddr_cntl_a_data_path_rst>.
    Related source file is "ddr_cntl_a_data_path_rst.v".
Unit <ddr_cntl_a_data_path_rst> synthesized.


Synthesizing Unit <ddr_cntl_a_data_write_0>.
    Related source file is "ddr_cntl_a_data_write_0.v".
WARNING:Xst:647 - Input <reset270_r> is never used.
WARNING:Xst:647 - Input <reset90_r> is never used.
WARNING:Xst:646 - Signal <write_en_P3> is assigned but never used.
WARNING:Xst:646 - Signal <write_data_m270_3> is assigned but never used.
WARNING:Xst:646 - Signal <write_data270_3> is assigned but never used.
WARNING:Xst:646 - Signal <write_en_int> is assigned but never used.
WARNING:Xst:646 - Signal <write_data_reg_dimm> is assigned but never used.
WARNING:Xst:646 - Signal <write_data_mask_reg_dimm> is assigned but never used.
    Found 1-bit register for signal <write_en_val>.
    Found 64-bit register for signal <write_data>.
    Found 64-bit register for signal <write_data1>.
    Found 64-bit register for signal <write_data2>.
    Found 64-bit register for signal <write_data270>.
    Found 32-bit register for signal <write_data270_1>.
    Found 32-bit register for signal <write_data270_2>.
    Found 64-bit register for signal <write_data3>.
    Found 64-bit register for signal <write_data4>.
    Found 8-bit register for signal <write_data_m1>.
    Found 8-bit register for signal <write_data_m2>.
    Found 8-bit register for signal <write_data_m270>.
    Found 4-bit register for signal <write_data_m270_1>.
    Found 4-bit register for signal <write_data_m270_2>.
    Found 8-bit register for signal <write_data_m3>.
    Found 8-bit register for signal <write_data_m4>.
    Found 8-bit register for signal <write_data_mask>.
    Found 1-bit register for signal <write_en_P1>.
    Summary:
	inferred 506 D-type flip-flop(s).
Unit <ddr_cntl_a_data_write_0> synthesized.


Synthesizing Unit <ddr_cntl_a_data_read_controller_0>.
    Related source file is "ddr_cntl_a_data_read_controller_0.v".
WARNING:Xst:1780 - Signal <rst_dqs_delay_2_n_1> is never used or assigned.
WARNING:Xst:1780 - Signal <write_data270_1> is never used or assigned.
WARNING:Xst:1780 - Signal <write_data270_2> is never used or assigned.
WARNING:Xst:1780 - Signal <rst_dqs_delay_3_n_1> is never used or assigned.
WARNING:Xst:1780 - Signal <ddr_dq_in> is never used or assigned.
WARNING:Xst:1780 - Signal <rst_dqs_delay_0_n_1> is never used or assigned.
WARNING:Xst:1780 - Signal <rst_dqs_delay_1_n_1> is never used or assigned.
    Found 4-bit comparator equal for signal <$n0000> created at line 305.
    Found 4-bit comparator equal for signal <$n0001> created at line 304.
    Found 4-bit register for signal <fifo_00_wr_addr_2d>.
    Found 4-bit register for signal <fifo_00_wr_addr_3d>.
    Found 4-bit register for signal <fifo_00_wr_addr_d>.
    Found 4-bit register for signal <fifo_01_wr_addr_2d>.
    Found 4-bit register for signal <fifo_01_wr_addr_3d>.
    Found 4-bit register for signal <fifo_01_wr_addr_d>.
    Found 1-bit register for signal <read_valid_data_r>.
    Found 1-bit register for signal <read_valid_data_r1>.
    Found 1-bit register for signal <u_data_val_r>.
    Summary:
	inferred  27 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <ddr_cntl_a_data_read_controller_0> synthesized.


Synthesizing Unit <ddr_cntl_a_data_read_0>.
    Related source file is "ddr_cntl_a_data_read_0.v".
WARNING:Xst:646 - Signal <read_valid_data_1_r2> is assigned but never used.
WARNING:Xst:1780 - Signal <fifop_rd_addr_r> is never used or assigned.
    Register <fifo11_rd_addr_r> equivalent to <fifo01_rd_addr_r> has been removed
    Register <fifo21_rd_addr_r> equivalent to <fifo01_rd_addr_r> has been removed
    Register <fifo31_rd_addr_r> equivalent to <fifo01_rd_addr_r> has been removed
    Register <fifo10_rd_addr_r> equivalent to <fifo00_rd_addr_r> has been removed
    Register <fifo20_rd_addr_r> equivalent to <fifo00_rd_addr_r> has been removed
    Register <fifo30_rd_addr_r> equivalent to <fifo00_rd_addr_r> has been removed
    Found 4-bit register for signal <fifo00_rd_addr_r>.
    Found 4-bit register for signal <fifo01_rd_addr_r>.
    Found 8-bit register for signal <fifo_00_data_out_r>.
    Found 8-bit register for signal <fifo_01_data_out_r>.
    Found 8-bit register for signal <fifo_10_data_out_r>.
    Found 8-bit register for signal <fifo_11_data_out_r>.
    Found 8-bit register for signal <fifo_20_data_out_r>.
    Found 8-bit register for signal <fifo_21_data_out_r>.
    Found 8-bit register for signal <fifo_30_data_out_r>.
    Found 8-bit register for signal <fifo_31_data_out_r>.
    Found 64-bit register for signal <first_sdr_data>.
    Found 1-bit register for signal <read_valid_data_1_r>.
    Found 1-bit register for signal <read_valid_data_1_r1>.
    Summary:
	inferred 138 D-type flip-flop(s).
Unit <ddr_cntl_a_data_read_0> synthesized.


Synthesizing Unit <ddr_cntl_a_iobs_0>.
    Related source file is "ddr_cntl_a_iobs_0.v".
Unit <ddr_cntl_a_iobs_0> synthesized.


Synthesizing Unit <ddr_cntl_a_infrastructure>.
    Related source file is "ddr_cntl_a_infrastructure.v".
    Found 5-bit register for signal <delay_sel_val1_r>.
    Found 1-bit register for signal <rst_calib1_r1>.
    Found 1-bit register for signal <rst_calib1_r2>.
    Summary:
	inferred   7 D-type flip-flop(s).
Unit <ddr_cntl_a_infrastructure> synthesized.


Synthesizing Unit <ddr_cntl_a_data_path_0>.
    Related source file is "ddr_cntl_a_data_path_0.v".
WARNING:Xst:646 - Signal <reset180_r> is assigned but never used.
Unit <ddr_cntl_a_data_path_0> synthesized.


Synthesizing Unit <ddr_cntl_a_controller_0>.
    Related source file is "ddr_cntl_a_controller_0.v".
WARNING:Xst:646 - Signal <ddr_casb5> is assigned but never used.
WARNING:Xst:646 - Signal <column_address_reg6> is assigned but never used.
WARNING:Xst:646 - Signal <config_reg<9:7>> is assigned but never used.
WARNING:Xst:646 - Signal <config_reg<3>> is assigned but never used.
WARNING:Xst:646 - Signal <DQS_enable4> is assigned but never used.
WARNING:Xst:646 - Signal <row_address_conflict> is assigned but never used.
WARNING:Xst:646 - Signal <read_enable_out_r> is assigned but never used.
WARNING:Xst:646 - Signal <DQS_reset4_clk0> is assigned but never used.
WARNING:Xst:646 - Signal <read_write_state> is assigned but never used.
WARNING:Xst:646 - Signal <wrburst_end_8> is assigned but never used.
WARNING:Xst:646 - Signal <wrburst_end_9> is assigned but never used.
WARNING:Xst:646 - Signal <GND> is assigned but never used.
WARNING:Xst:646 - Signal <ddr_rasb5> is assigned but never used.
WARNING:Xst:646 - Signal <read_rcd_end> is assigned but never used.
WARNING:Xst:646 - Signal <read_cmd_reg> is assigned but never used.
WARNING:Xst:646 - Signal <ddr_web5> is assigned but never used.
WARNING:Xst:646 - Signal <ddr_ba5> is assigned but never used.
WARNING:Xst:646 - Signal <dly_dqs_div_r> is assigned but never used.
WARNING:Xst:646 - Signal <ddr_address5> is assigned but never used.
WARNING:Xst:646 - Signal <write_cmd> is assigned but never used.
WARNING:Xst:646 - Signal <write_cmd8> is assigned but never used.
WARNING:Xst:646 - Signal <command_reg> is assigned but never used.
    Register <wrburst_end_1> equivalent to <rdburst_end_1> has been removed
    Register <wrburst_end_2> equivalent to <rdburst_end_2> has been removed
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <next_state> of Case statement line 1101 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <next_state> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <next_state>.
    Using one-hot encoding for signal <next_state1>.
    Found 4x1-bit ROM for signal <address_config<8>>.
    Found 1-bit register for signal <ar_done>.
    Found 2-bit register for signal <ddr_ba_cntrl>.
    Found 13-bit register for signal <ddr_address_cntrl>.
    Found 1-bit register for signal <write_enable>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0022>.
    Found 11-bit adder for signal <$n0026> created at line 597.
    Found 3-bit adder for signal <$n0027> created at line 918.
    Found 8-bit subtractor for signal <$n0028> created at line 924.
    Found 3-bit subtractor for signal <$n0029> created at line 521.
    Found 2-bit subtractor for signal <$n0030> created at line 502.
    Found 5-bit subtractor for signal <$n0031> created at line 512.
    Found 4-bit subtractor for signal <$n0032> created at line 560.
    Found 3-bit subtractor for signal <$n0033> created at line 719.
    Found 2-bit subtractor for signal <$n0034> created at line 529.
    Found 3-bit subtractor for signal <$n0035> created at line 544.
    Found 2-bit subtractor for signal <$n0036> created at line 548.
    Found 4-bit subtractor for signal <$n0037> created at l