ddr_cntl_a.syr

arm控制FPGA的DDR测试代码

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.01 / 0.41 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: ddr_cntl_a.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ddr_cntl_a.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ddr_cntl_a"
Output Format                      : NGC
Target Device                      : xc3s4000-5-fg900

---- Source Options
Top Module Name                    : ddr_cntl_a
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : ddr_cntl_a.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "ddr_cntl_a_wr_gray_cntr.v" in library work
Compiling verilog file "ddr_cntl_a_s3_dqs_iob.v" in library work
Module <ddr_cntl_a_wr_gray_cntr> compiled
Compiling verilog file "ddr_cntl_a_s3_ddr_iob.v" in library work
Module <ddr_cntl_a_s3_dqs_iob> compiled
Compiling verilog file "ddr_cntl_a_rd_gray_cntr.v" in library work
Module <ddr_cntl_a_s3_ddr_iob> compiled
Compiling verilog file "ddr_cntl_a_fifo_1_wr_en_0.v" in library work
Module <ddr_cntl_a_rd_gray_cntr> compiled
Compiling verilog file "ddr_cntl_a_fifo_0_wr_en_0.v" in library work
Module <ddr_cntl_a_fifo_1_wr_en_0> compiled
Compiling verilog file "ddr_cntl_a_dqs_delay.v" in library work
Module <ddr_cntl_a_fifo_0_wr_en_0> compiled
Compiling verilog file "ddr_cntl_a_ddr1_dm_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_dqs_delay> compiled
Compiling verilog file "ddr_cntl_a_RAM8D_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_ddr1_dm_0> compiled
Compiling verilog file "ddr_cntl_a_infrastructure_iobs_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_RAM8D_0> compiled
Compiling verilog file "ddr_cntl_a_data_write_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_infrastructure_iobs_0> compiled
Compiling verilog file "ddr_cntl_a_data_read_controller_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_data_write_0> compiled
Compiling verilog file "ddr_cntl_a_data_read_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_data_read_controller_0> compiled
Compiling verilog file "ddr_cntl_a_data_path_rst.v" in library work
Module <ddr_cntl_a_data_read_0> compiled
Compiling verilog file "ddr_cntl_a_data_path_iobs_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_data_path_rst> compiled
Compiling verilog file "ddr_cntl_a_controller_iobs_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_data_path_iobs_0> compiled
Compiling verilog file "ddr_cntl_a_tap_dly_0.v" in library work
Module <ddr_cntl_a_controller_iobs_0> compiled
Compiling verilog file "ddr_cntl_a_mybufg_0.v" in library work
Module <ddr_cntl_a_tap_dly_0> compiled
Compiling verilog file "ddr_cntl_a_lfsr32_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_mybufg_0> compiled
Compiling verilog file "ddr_cntl_a_iobs_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_lfsr32_0> compiled
Compiling verilog file "ddr_cntl_a_infrastructure.v" in library work
Module <ddr_cntl_a_iobs_0> compiled
Compiling verilog file "ddr_cntl_a_data_path_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_infrastructure> compiled
Compiling verilog file "ddr_cntl_a_controller_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_data_path_0> compiled
Compiling verilog file "ddr_cntl_a_cmp_data_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_controller_0> compiled
Compiling verilog file "ddr_cntl_a_cmd_fsm_0.v" in library work
Module <ddr_cntl_a_cmp_data_0> compiled
Compiling verilog file "ddr_cntl_a_cal_ctl_0.v" in library work
Module <ddr_cntl_a_cmd_fsm_0> compiled
Compiling verilog file "ddr_cntl_a_addr_gen_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_cal_ctl_0> compiled
Compiling verilog file "ddr_cntl_a_top_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_addr_gen_0> compiled
Compiling verilog file "ddr_cntl_a_ddr1_test_bench_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_top_0> compiled
Compiling verilog file "ddr_cntl_a_clk_dcm.v" in library work
Module <ddr_cntl_a_ddr1_test_bench_0> compiled
Compiling verilog file "ddr_cntl_a_cal_top.v" in library work
Module <ddr_cntl_a_clk_dcm> compiled
Compiling verilog file "ddr_cntl_a_main_0.v" in library work
Compiling verilog include file "ddr_cntl_a_parameters_0.v"
Module <ddr_cntl_a_cal_top> compiled
Compiling verilog file "ddr_cntl_a_infrastructure_top.v" in library work
Module <ddr_cntl_a_main_0> compiled
Compiling verilog file "ddr_cntl_a.v" in library work
Module <ddr_cntl_a_infrastructure_top> compiled
Module <ddr_cntl_a> compiled
No errors in compilation
Analysis of file <"ddr_cntl_a.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <ddr_cntl_a>.
Module <ddr_cntl_a> is correct for synthesis.
 
Analyzing module <ddr_cntl_a_main_0>.
Module <ddr_cntl_a_main_0> is correct for synthesis.
 
Analyzing module <ddr_cntl_a_top_0>.
Module <ddr_cntl_a_top_0> is correct for synthesis.
 
Analyzing module <ddr_cntl_a_controller_0>.
	IDLE = 4'b0000
	PRECHARGE = 4'b0001
	LOAD_MODE_REG = 4'b0010
	AUTO_REFRESH = 4'b0011
	ACTIVE = 4'b0100
	FIRST_WRITE = 4'b0101
	WRITE_WAIT = 4'b0110
	BURST_WRITE = 4'b0111
	READ_AFTER_WRITE = 4'b1000
	PRECHARGE_AFTER_WRITE = 4'b1001
	PRECHARGE_AFTER_WRITE_2 = 4'b1010
	READ_WAIT = 4'b1011
	BURST_READ = 4'b1100
	BURST_STOP = 4'b1101
	ACTIVE_WAIT = 4'b1110