ddr_cntl_a.ucf

arm控制FPGA的DDR测试代码

############################################################################
##
##  Xilinx, Inc. 2006            www.xilinx.com  
##  Tue October 17 9:21: 2006
##
##  
############################################################################
##  File name :       ddr_cntl_a.ucf
## 
##  Generated by  spartan3 released on April 03 2006
##  Description :     Constraints file
##                    targetted to xc3s4000-4 fg900 
##
############################################################################

############################################################################
# Clock constraints                                                        #
############################################################################
NET "infrastructure_top0/sys_clk_ibuf" TNM_NET = FFS(*) "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK"  7.518797  ns HIGH 50 %;

############################################################################
NET "infrastructure_top0/wait_200*" TIG;
NET "infrastructure_top0/wait_clk90" TIG;
NET "infrastructure_top0/sys_rst*"   TIG;

NET "main_00/top0/reset90_r" TIG;

NET "main_00/top0/controller0/rst_calib*" TIG;
NET "main_00/top0/infrastructure0/delay_sel_val*" TIG;
NET "main_00/top0/infrastructure0/rst_calib*" TIG;
##INST "*/cal_top0/cal_ctl0/un1_tapForDqs*" TIG;
NET "infrastructure_top0/reset_in" TIG;
NET "infrastructure_top0/sys_rst*" TIG;
NET "*/controller0/rst0*" TIG;
NET "*/controller0/rst180*" TIG;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay*_col*" TIG;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed*" TIG;


#######################################################################################################################
# Calibration Circuit Constraints #
#######################################################################################################################
# Placement constraints for luts in tap delay ckt #
#######################################################################################################################

INST  "infrastructure_top0/cal_top0/tap_dly0/l0"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l1"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l2"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l3"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l4"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l5"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l6"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l7"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  
INST  "infrastructure_top0/cal_top0/tap_dly0/l8"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l9"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l10"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l11"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l12"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l13"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l14"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l15"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l16"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l17"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l18"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l19"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l20"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l21"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l22"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l23"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l24"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l25"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l26"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l27"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l28"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l29"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l30"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l31"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

#######################################################################################################################
# Placement constraints for first stage flops in tap delay ckt #
#######################################################################################################################
 
INST  "infrastructure_top0/cal_top0/tap_dly0/r0"   U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r1"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r2"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r3"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r4"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r5"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r6"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r7"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r8"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r9"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r10"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r11"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r12"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r13"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r14"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r15"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r16"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r17"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r18"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r19"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r20"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r21"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r22"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r23"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r24"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r25"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r26"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r27"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r28"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r29"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r30"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/r31"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

#######################################################################################################################
# BEL constraints for luts in tap delay ckt #
#######################################################################################################################

INST "infrastructure_top0/cal_top0/tap_dly0/l0" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l1" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l2" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l3" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l4" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l5" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l6" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l7" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l8" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l9" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;  
INST "infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;


 ######################################################################################
 ##### constraints to have the inverter connetion wire length to be the same   ########
 ###### the following  constraints are independent of frequency  ######################
 ######################################################################################

 ###### maxdelay of 400 ps will not be met. This constraint is just to get a better delay####
 NET "infrastructure_top0/cal_top0/tap_dly0/tap[7]"  MAXDELAY = 400ps;
 NET "infrastructure_top0/cal_top0/tap_dly0/tap[15]"  MAXDELAY = 400ps;
 NET "infrastructure_top0/cal_top0/tap_dly0/tap[23]"  MAXDELAY = 400ps;
 INST "main_00/top0/controller0/rst_iob_out" IOB = TRUE;
 
 ##################################################################
 ##### constraints from the dqs pin ########
 ##################################################################