ddr_cntl_a_map.mrp

arm控制FPGA的DDR测试代码

has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob17/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob16/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob15/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob14/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob13/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob12/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob11/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob10/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob9/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob8/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob7/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob6/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob5/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob4/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob3/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/N0" is sourceless and
has been removed.
The signal "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_en_inst/N0"
is sourceless and has been removed.
The signal "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_en_inst/N0"
is sourceless and has been removed.
The signal "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_en_inst/N0"
is sourceless and has been removed.
The signal "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_en_inst/N0"
is sourceless and has been removed.
The signal "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_en_inst/N0"
is sourceless and has been removed.
The signal "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_en_inst/N0"
is sourceless and has been removed.
The signal "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_en_inst/N0"
is sourceless and has been removed.
The signal "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_en_inst/N0"
is sourceless and has been removed.
The signal "main_00/top0/data_path0/data_path_rst0/reset180_r" is sourceless and
has been removed.
The signal "main_00/top0/data_path0/data_path_rst0/_n0002" is sourceless and has
been removed.
 Sourceless block "main_00/top0/data_path0/data_path_rst0/rst180_r" (FF) removed.
The signal "main_00/top0/data_path0/data_path_rst0/_n0003" is sourceless and has
been removed.
The signal "main_00/ddr1_test_bench0/data_valid_out" is sourceless and has been
removed.
The signal "main_00/ddr1_test_bench0/lfsr_data_r<56>" is sourceless and has been
removed.
The signal "main_00/ddr1_test_bench0/lfsr_data_r<48>" is sourceless and has been
removed.
The signal "main_00/ddr1_test_bench0/lfsr_data_r<40>" is sourceless and has been
removed.
The signal "main_00/ddr1_test_bench0/lfsr_data_r<32>" is sourceless and has been
removed.
The signal "main_00/ddr1_test_bench0/lfsr_data_r<24>" is sourceless and has been
removed.
The signal "main_00/ddr1_test_bench0/lfsr_data_r<16>" is sourceless and has been
removed.
The signal "main_00/ddr1_test_bench0/lfsr_data_r<8>" is sourceless and has been
removed.
The signal "main_00/ddr1_test_bench0/lfsr_data_r<0>" is sourceless and has been
removed.

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "sys_rst180" is unused and has been removed.
The signal "delay_sel_val<0>" is unused and has been removed.
Unused block "infrastructure_top0/sys_rst270_o" (SFF) removed.
Unused block "main_00/top0/data_path0/data_path_rst0/_n00021" (ROM) removed.
Unused block "main_00/top0/data_path0/data_path_rst0/_n00031" (ROM) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		infrastructure_top0/XST_GND
VCC 		infrastructure_top0/XST_VCC
VCC 		infrastructure_top0/cal_top0/XST_VCC
VCC 		infrastructure_top0/cal_top0/cal_ctl0/XST_VCC
VCC 		infrastructure_top0/cal_top0/tap_dly0/XST_VCC
GND 		infrastructure_top0/clk_dcm0/XST_GND
VCC 		main_00/ddr1_test_bench0/XST_VCC
GND 		main_00/ddr1_test_bench0/INST1/XST_GND
VCC 		main_00/ddr1_test_bench0/INST1/XST_VCC
GND 		main_00/ddr1_test_bench0/INST7/XST_GND
VCC 		main_00/ddr1_test_bench0/INST7/XST_VCC
VCC 		main_00/ddr1_test_bench0/INST_2/XST_VCC
GND 		main_00/top0/controller0/XST_GND
VCC 		main_00/top0/controller0/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/fifo_00_wr_en_inst/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/fifo_01_wr_en_inst/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/fifo_10_wr_en_inst/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/fifo_11_wr_en_inst/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/fifo_20_wr_en_inst/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/fifo_21_wr_en_inst/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/fifo_30_wr_en_inst/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/fifo_31_wr_en_inst/XST_VCC
VCC 		main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/XST_VCC
GND 		main_00/top0/data_path0/data_write0/XST_GND
VCC 		main_00/top0/data_path0/data_write0/XST_VCC
FD 		main_00/top0/iobs0/controller_iobs0/iob_addr11
   optimized to 0
FD 		main_00/top0/iobs0/controller_iobs0/iob_addr9
   optimized to 0
FD 		main_00/top0/iobs0/controller_iobs0/iob_ba2
   optimized to 0
GND 		main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/XST_GND
VCC 		main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob0/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob1/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob10/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob11/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob12/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob13/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob14/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob15/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob16/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob17/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob18/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob19/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob2/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob20/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob21/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob22/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob23/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob24/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob25/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob26/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob27/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob28/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob29/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob3/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob30/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob31/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob4/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob5/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob6/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob7/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob8/XST_VCC
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob9/XST_VCC
GND 		main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/XST_GND
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/XST_VCC
GND 		main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/XST_GND
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/XST_VCC
GND 		main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/XST_GND
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/XST_VCC
GND 		main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/XST_GND
VCC 		main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/XST_VCC
GND 		main_00/top0/iobs0/infrastructure_iobs0/XST_GND
VCC 		main_00/top0/iobs0/infrastructure_iobs0/XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.