ddr_cntl_a_map.mrp

arm控制FPGA的DDR测试代码

   main_00/top0/data_path0/data_read_controller0/dqs3_delayed_col0_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs2_delayed_col0_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs1_delayed_col0_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read_controller0/dqs0_delayed_col0_n is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs3_delayed_col0_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs3_delayed_col1_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs2_delayed_col0_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs2_delayed_col1_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs1_delayed_col0_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs1_delayed_col1_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs0_delayed_col0_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/top0/data_path0/data_read0/dqs0_delayed_col1_n is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   main_00/ddr1_test_bench0/_n0003 is sourced by a combinatorial pin. This is
   not good design practice. Use the CE pin to control the loading of data into
   the flip-flop.
WARNING:PhysDesignRules:367 - The signal <GLOBAL_LOGIC1> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <SYS_CLKb_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:767 - Unexpected DCM configuration. The signal on the
   CLKIN pin of DCM comp
   infrastructure_top0/clk_dcm0/infrastructure_top0/clk_dcm0/DCM_INST1 is not
   driven by an IOB or BUFGMUX therefore the phase relationship of output clocks
   to CLKIN cannot be guaranteed.
WARNING:PhysDesignRules:739 - Unexpected DCM feedback loop. The signal
   infrastructure_top0/clk_dcm0/clk on the CLKFB pin of comp
   infrastructure_top0/clk_dcm0/infrastructure_top0/clk_dcm0/DCM_INST1 is not
   driven by an IOB or BUFGMUX therefore the phase relationship of output clocks
   to CLKIN cannot be guaranteed.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "infrastructure_top0/clk_dcm0/BUFG_CLK90/u1" (output
   signal=clk90_0)
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "infrastructure_top0/clk_dcm0/BUFG_CLK0/u1" (output signal=clk_0)
INFO:MapLib:159 - Net Timing constraints on signal rst_dqs_div_in are pushed
   forward through input buffer.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.
INFO:Pack:1716 - Initializing temperature to 85.000 Celcius. (default - Range:
   0.000 to 85.000 Celcius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Timing:2802 - Read 274 constraints.  If you are experiencing memory or
   runtime issues it may help to consolidate some of these constraints.  For
   more details please see solution 10784 at support.xilinx.com
INFO:Pack:1650 - Map created a placed design.
INFO:Timing:2802 - Read 274 constraints.  If you are experiencing memory or
   runtime issues it may help to consolidate some of these constraints.  For
   more details please see solution 10784 at support.xilinx.com

Section 4 - Removed Logic Summary
---------------------------------
   7 block(s) removed
 188 block(s) optimized away
  76 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "infrastructure_top0/sys_rst270_1" is sourceless and has been
removed.
 Sourceless block "infrastructure_top0/sys_rst270" (SFF) removed.
  The signal "sys_rst270" is sourceless and has been removed.
   Sourceless block "main_00/top0/data_path0/data_path_rst0/rst270_r" (FF) removed.
    The signal "main_00/top0/data_path0/reset270_r" is sourceless and has been
removed.
The signal "infrastructure_top0/sys_rst270_o" is sourceless and has been
removed.
 Sourceless block "infrastructure_top0/sys_rst270_1" (SFF) removed.
The signal "infrastructure_top0/delay_sel_val1_val_tb<4>" is sourceless and has
been removed.
The signal "infrastructure_top0/delay_sel_val1_val_tb<1>" is sourceless and has
been removed.
The signal "infrastructure_top0/delay_sel_val1_val_tb<0>" is sourceless and has
been removed.
The signal "main_00/auto_ref_req" is sourceless and has been removed.
The signal "main_00/ar_done_val1" is sourceless and has been removed.
The signal "main_00/u1_config_parms<9>" is sourceless and has been removed.
The signal "main_00/u1_config_parms<8>" is sourceless and has been removed.
The signal "main_00/u1_config_parms<7>" is sourceless and has been removed.
The signal "main_00/u1_config_parms<3>" is sourceless and has been removed.
The signal "main_00/user_cmd1<0>" is sourceless and has been removed.
The signal "main_00/top0/ddr_address_cntrl<11>" is sourceless and has been
removed.
The signal "main_00/top0/write_en_val" is sourceless and has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/vcc" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/ddr1_dm0/gnd" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob3/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob2/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob1/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_dqs_iob0/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob31/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob30/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob29/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob28/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob27/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob26/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob25/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob24/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob23/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob22/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob21/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob20/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob19/N0" is sourceless and
has been removed.
The signal "main_00/top0/iobs0/datapath_iobs0/s3_ddr_iob18/N0" is sourceless and