map.xmsgs

arm控制FPGA的DDR测试代码

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<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">SYS_CLKb_IBUF</arg> has no load.
</msg>

<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">83</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">infrastructure_top0/delay_sel_val1_val_tb&lt;4&gt;,
infrastructure_top0/delay_sel_val1_val_tb&lt;1&gt;,
infrastructure_top0/delay_sel_val1_val_tb&lt;0&gt;,
main_00/ar_done_val1,
main_00/u1_config_parms&lt;9&gt;</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>

<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFG symbol &quot;infrastructure_top0/clk_dcm0/BUFG_CLK90/u1&quot; (output signal=clk90_0)</arg>
</msg>

<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFG symbol &quot;infrastructure_top0/clk_dcm0/BUFG_CLK0/u1&quot; (output signal=clk_0)</arg>
</msg>

<msg type="info" file="MapLib" num="159" delta="unknown" >Net Timing constraints on signal <arg fmt="%s" index="1">rst_dqs_div_in</arg> are pushed forward through input buffer.
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>

<msg type="warning" file="LIT" num="175" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;infrastructure_top0/clk_dcm0/BUFG_CLK0/physical_group_O/u1&quot; (output signal=clk_0)</arg> has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
<arg fmt="%s" index="2">Pin I0 of main_00/ddr1_test_bench0/_n00031
Pin D of infrastructure_top0/cal_top0/tap_dly0/r0
Pin D of infrastructure_top0/cal_top0/tap_dly0/r1
Pin D of infrastructure_top0/cal_top0/tap_dly0/r2
Pin D of infrastructure_top0/cal_top0/tap_dly0/r3</arg>
</msg>

<msg type="warning" file="Pack" num="1236" delta="unknown" >The register <arg fmt="%s" index="1">main_00/top0/controller0/rst_iob_out</arg> has the property IOB=TRUE, but failed to join the output side of an I/O component. <arg fmt="%z" index="2">Symbol main_00/top0/controller0/rst_iob_out is not under the same hierarchy region as symbol main_00/top0/iobs0/controller_iobs0/rst_iob_outbuf. There are three ways to fix the problem:
1. Put both symbols under the same hierarchy region and process the design. If the I/O buffer is being inferred by the synthesis tool, it is suggested to code I/O registers on the top level of code. If this can not be done, it is suggested to instantiate the proper I/O buffer in the lower level of code and disable I/O buffer inference for that port in the design.
2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block main_00/top0/controller0 and main_00/top0/iobs0/controller_iobs0 in the UCF file.
3. Run map with the option -ignore_keep_hierarchy. This option will dissolve all hierarchy in the design.
</arg>
</msg>

<msg type="warning" file="Pack" num="1237" delta="unknown" >The register <arg fmt="%s" index="1">main_00/top0/controller0/rst_iob_out</arg> failed to join the output side of an I/O component. <arg fmt="%z" index="2">Symbol main_00/top0/controller0/rst_iob_out is not under the same hierarchy region as symbol main_00/top0/iobs0/controller_iobs0/rst_iob_outbuf. There are three ways to fix the problem:
1. Put both symbols under the same hierarchy region and process the design. If the I/O buffer is being inferred by the synthesis tool, it is suggested to code I/O registers on the top level of code. If this can not be done, it is suggested to instantiate the proper I/O buffer in the lower level of code and disable I/O buffer inference for that port in the design.
2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block main_00/top0/controller0 and main_00/top0/iobs0/controller_iobs0 in the UCF file.
3. Run map with the option -ignore_keep_hierarchy. This option will dissolve all hierarchy in the design.
</arg>
</msg>

<msg type="warning" file="Pack" num="1237" delta="unknown" >The register <arg fmt="%s" index="1">main_00/ddr1_test_bench0/INST3/led_state</arg> failed to join the output side of an I/O component. <arg fmt="%z" index="2">Symbol main_00/ddr1_test_bench0/INST3/led_state is not under the same hierarchy region as symbol cntrl0_led_error_output1_OBUF. There are three ways to fix the problem:
1. Put both symbols under the same hierarchy region and process the design. If the I/O buffer is being inferred by the synthesis tool, it is suggested to code I/O registers on the top level of code. If this can not be done, it is suggested to instantiate the proper I/O buffer in the lower level of code and disable I/O buffer inference for that port in the design.
2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block main_00/ddr1_test_bench0/INST3 in the UCF file.
3. Run map with the option -ignore_keep_hierarchy. This option will dissolve all hierarchy in the design.
</arg>
</msg>

<msg type="info" file="Pack" num="1716" delta="unknown" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celcius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celcius)
</msg>

<msg type="info" file="Pack" num="1720" delta="unknown" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>

<msg type="info" file="Timing" num="2802" delta="unknown" >Read <arg fmt="%d" index="1">274</arg> constraints.  If you are experiencing memory or runtime issues it may help to consolidate some of these constraints.  For more details please see solution 10784 at support.xilinx.com</msg>

<msg type="info" file="Pack" num="1650" delta="unknown" >Map created a placed design.
</msg>

<msg type="info" file="Timing" num="2802" delta="unknown" >Read <arg fmt="%d" index="1">274</arg> constraints.  If you are experiencing memory or runtime issues it may help to consolidate some of these constraints.  For more details please see solution 10784 at support.xilinx.com</msg>

<msg type="info" file="Timing" num="2761" delta="unknown" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs3_delayed_col1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net main_00/top0/data_path0/dqs2_delayed_col0 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>