📄 ddr_cntl_a.par
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|main_00/top0/data_pa | | | | | ||th0/data_read_contro | | | | | ||ller0/dqs3_delayed_c | | | | | || ol1_n | Local| | 1 | 0.000 | 0.307 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read_contro | | | | | ||ller0/dqs2_delayed_c | | | | | || ol1_n | Local| | 1 | 0.000 | 0.307 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read_contro | | | | | ||ller0/dqs1_delayed_c | | | | | || ol1_n | Local| | 1 | 0.000 | 0.307 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read_contro | | | | | ||ller0/dqs0_delayed_c | | | | | || ol1_n | Local| | 1 | 0.000 | 0.888 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read_contro | | | | | ||ller0/dqs3_delayed_c | | | | | || ol0_n | Local| | 2 | 0.000 | 0.443 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read_contro | | | | | ||ller0/dqs2_delayed_c | | | | | || ol0_n | Local| | 2 | 0.000 | 1.200 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read_contro | | | | | ||ller0/dqs1_delayed_c | | | | | || ol0_n | Local| | 2 | 0.000 | 0.443 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read_contro | | | | | ||ller0/dqs0_delayed_c | | | | | || ol0_n | Local| | 2 | 0.000 | 0.459 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read0/dqs3_ | | | | | || delayed_col0_n | Local| | 4 | 0.711 | 1.387 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read0/dqs3_ | | | | | || delayed_col1_n | Local| | 4 | 1.199 | 1.816 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read0/dqs2_ | | | | | || delayed_col0_n | Local| | 4 | 0.003 | 0.451 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read0/dqs2_ | | | | | || delayed_col1_n | Local| | 4 | 0.998 | 1.891 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read0/dqs1_ | | | | | || delayed_col0_n | Local| | 4 | 1.535 | 2.205 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read0/dqs1_ | | | | | || delayed_col1_n | Local| | 4 | 0.600 | 1.337 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read0/dqs0_ | | | | | || delayed_col0_n | Local| | 4 | 0.122 | 1.046 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/data_read0/dqs0_ | | | | | || delayed_col1_n | Local| | 4 | 0.301 | 1.199 |+---------------------+--------------+------+------+------------+-------------+|main_00/ddr1_test_be | | | | | || nch0/_n0003 | Local| | 10 | 0.234 | 3.706 |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays. The Delay Summary ReportThe NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 1.497 The MAXIMUM PIN DELAY IS: 10.427 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 7.045 Listing Pin Delays by value: (nsec) d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 11.00 d >= 11.00 --------- --------- --------- --------- --------- --------- 3520 734 141 26 31 0Timing Score: 160565INFO:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your
design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place & Route Static Timing Report"). Go to the failing constraint(s) and select the "Timing Improvement Wizard" link for suggestions to correct each problem. Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations" (ISE process "Multi Pass Place & Route"). Use the Xilinx "xplorer" script to try special combinations of options known to produce very good results. See http://www.xilinx.com/xplorer for details. Visit the Xilinx technical support web at http://support.xilinx.com and go to either "Troubleshoot->Tech Tips->Timing & Constraints" or " TechXclusives->Timing Closure" for tips and suggestions for meeting timing in your design.Number of Timing Constraints that were not applied: 27Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------ Constraint | Requested | Actual | Logic | Absolute |Number of | | | Levels | Slack |errors ------------------------------------------------------------------------------------------------------* TS_infrastructure_top0_clk_dcm0_clk0dcm = | 0.000ns | -3.864ns | 1 | -3.864ns | 18 PERIOD TIMEGRP "infrastructure_t | | | | | op0_clk_dcm0_clk0dcm" TS_SYS_CLK HIGH 50% | | | | | HOLD ERROR | | | | | ------------------------------------------------------------------------------------------------------* TS_infrastructure_top0_clk_dcm0_clk0dcm = | 7.518ns | 24.812ns | 1 | -17.294ns | 1 PERIOD TIMEGRP "infrastructure_t | | | | | op0_clk_dcm0_clk0dcm" TS_SYS_CLK HIGH 50% | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/dqs_int_delay_in0" MAXD | 0.700ns | 3.848ns | 0 | -3.148ns | 1 ELAY = 0.7 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/dqs_int_delay_in1" MAXD | 0.700ns | 3.777ns | 0 | -3.077ns | 1 ELAY = 0.7 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/dqs_int_delay_in2" MAXD | 0.700ns | 3.751ns | 0 | -3.051ns | 1 ELAY = 0.7 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/dqs_int_delay_in3" MAXD | 0.700ns | 3.521ns | 0 | -2.821ns | 1 ELAY = 0.7 ns | | | | | ------------------------------------------------------------------------------------------------------* NET "main_00/top0/data_path0/data_read_co | 0.160ns | 0.315ns | 0 | -0.155ns | 1 ⌨️ 快捷键说明
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