clock_vhd.sdo

基于SMART-I实验平台的时钟电路设计与实现

        (PORT clk (3964:3964:3964) (3964:3964:3964))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_10s\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (460:460:460) (460:460:460))
        (PORT datab (416:416:416) (416:416:416))
        (PORT datac (466:466:466) (466:466:466))
        (PORT datad (431:431:431) (431:431:431))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_10s\[2\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (834:834:834) (834:834:834))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_10s\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1158:1158:1158) (1158:1158:1158))
        (PORT clk (3964:3964:3964) (3964:3964:3964))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_10s\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (460:460:460) (460:460:460))
        (PORT datab (417:417:417) (417:417:417))
        (PORT datac (464:464:464) (464:464:464))
        (PORT datad (434:434:434) (434:434:434))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_10s\[1\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (832:832:832) (832:832:832))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_10s\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1158:1158:1158) (1158:1158:1158))
        (PORT clk (3964:3964:3964) (3964:3964:3964))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_10s\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (460:460:460) (460:460:460))
        (PORT datab (417:417:417) (417:417:417))
        (PORT datac (459:459:459) (459:459:459))
        (PORT datad (438:438:438) (438:438:438))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_10s\[3\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (827:827:827) (827:827:827))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_10s\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1158:1158:1158) (1158:1158:1158))
        (PORT clk (3964:3964:3964) (3964:3964:3964))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_1s\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (476:476:476) (476:476:476))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_1s\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1156:1156:1156) (1156:1156:1156))
        (PORT clk (1009:1009:1009) (1009:1009:1009))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_1s\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (448:448:448) (448:448:448))
        (PORT datac (466:466:466) (466:466:466))
        (PORT datad (477:477:477) (477:477:477))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_1s\[2\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (834:834:834) (834:834:834))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_1s\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1156:1156:1156) (1156:1156:1156))
        (PORT clk (1009:1009:1009) (1009:1009:1009))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_1s\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (458:458:458) (458:458:458))
        (PORT datab (439:439:439) (439:439:439))
        (PORT datac (468:468:468) (468:468:468))
        (PORT datad (476:476:476) (476:476:476))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_1s\[1\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (836:836:836) (836:836:836))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_1s\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1156:1156:1156) (1156:1156:1156))
        (PORT clk (1009:1009:1009) (1009:1009:1009))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_1s\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (451:451:451) (451:451:451))
        (PORT datab (450:450:450) (450:450:450))
        (PORT datac (467:467:467) (467:467:467))
        (PORT datad (478:478:478) (478:478:478))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_1s\[3\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (835:835:835) (835:835:835))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_1s\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1156:1156:1156) (1156:1156:1156))
        (PORT clk (1009:1009:1009) (1009:1009:1009))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Mux0\~122_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1234:1234:1234) (1234:1234:1234))
        (PORT datab (2046:2046:2046) (2046:2046:2046))
        (PORT datac (463:463:463) (463:463:463))
        (PORT datad (1784:1784:1784) (1784:1784:1784))
        (IOPATH dataa combout (454:454:454) (454:454:454))
        (IOPATH datab combout (340:340:340) (340:340:340))
        (IOPATH datac combout (225:225:225) (225:225:225))
        (IOPATH datad combout (88:88:88) (88:88:88))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_1h\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (448:448:448) (448:448:448))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_1h\[0\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (816:816:816) (816:816:816))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_1h\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1155:1155:1155) (1155:1155:1155))
        (PORT clk (4222:4222:4222) (4222:4222:4222))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_10h\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (451:451:451) (451:451:451))
        (PORT datab (425:425:425) (425:425:425))
        (PORT datac (462:462:462) (462:462:462))
        (PORT datad (881:881:881) (881:881:881))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_10h\[0\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (830:830:830) (830:830:830))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_10h\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1155:1155:1155) (1155:1155:1155))
        (PORT clk (4087:4087:4087) (4087:4087:4087))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_10h\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (449:449:449) (449:449:449))
        (PORT datab (432:432:432) (432:432:432))
        (PORT datac (463:463:463) (463:463:463))
        (PORT datad (882:882:882) (882:882:882))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_10h\[3\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (831:831:831) (831:831:831))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_10h\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1155:1155:1155) (1155:1155:1155))
        (PORT clk (4087:4087:4087) (4087:4087:4087))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_10h\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (449:449:449) (449:449:449))
        (PORT datab (429:429:429) (429:429:429))
        (PORT datac (461:461:461) (461:461:461))
        (PORT datad (881:881:881) (881:881:881))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_10h\[1\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (829:829:829) (829:829:829))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_10h\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1155:1155:1155) (1155:1155:1155))
        (PORT clk (4087:4087:4087) (4087:4087:4087))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_10h\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (437:437:437) (437:437:437))
        (PORT datab (430:430:430) (430:430:430))
        (PORT datac (463:463:463) (463:463:463))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_10h\[2\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (831:831:831) (831:831:831))
      )
    )
  )