clock_vhd.sdo

基于SMART-I实验平台的时钟电路设计与实现

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1C3T144C6 Package TQFP144
// 

// 
// This SDF file should be used for PrimeTime (VHDL) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "clock")
  (DATE "11/04/2006 14:20:49")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\clk\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1130:1130:1130) (1130:1130:1130))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_counter_1h\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (345:345:345) (345:345:345))
        (PORT datab (431:431:431) (431:431:431))
        (PORT datac (453:453:453) (453:453:453))
        (PORT datad (492:492:492) (492:492:492))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_counter_1h\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (821:821:821) (821:821:821))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_counter_1h\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (691:691:691) (691:691:691))
        (PORT clk (3598:3598:3598) (3598:3598:3598))
        (PORT ena (1569:1569:1569) (1569:1569:1569))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (SETUP ena (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
      (HOLD ena (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_counter_10s\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (454:454:454) (454:454:454))
        (PORT datab (349:349:349) (349:349:349))
        (PORT datac (422:422:422) (422:422:422))
        (PORT datad (477:477:477) (477:477:477))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_counter_10s\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (790:790:790) (790:790:790))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_counter_10s\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (691:691:691) (691:691:691))
        (PORT clk (1009:1009:1009) (1009:1009:1009))
        (PORT ena (1605:1605:1605) (1605:1605:1605))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (SETUP ena (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
      (HOLD ena (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_counter_10h\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (409:409:409) (409:409:409))
        (PORT datab (1433:1433:1433) (1433:1433:1433))
        (PORT datac (359:359:359) (359:359:359))
        (PORT datad (550:550:550) (550:550:550))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_counter_10h\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (727:727:727) (727:727:727))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_counter_10h\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (691:691:691) (691:691:691))
        (PORT clk (4222:4222:4222) (4222:4222:4222))
        (PORT ena (1591:1591:1591) (1591:1591:1591))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (SETUP ena (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
      (HOLD ena (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_counter_10m\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (424:424:424) (424:424:424))
        (PORT datab (307:307:307) (307:307:307))
        (PORT datac (426:426:426) (426:426:426))
        (PORT datad (469:469:469) (469:469:469))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_counter_10m\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (794:794:794) (794:794:794))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_counter_10m\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (691:691:691) (691:691:691))
        (PORT clk (3399:3399:3399) (3399:3399:3399))
        (PORT ena (1579:1579:1579) (1579:1579:1579))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (SETUP ena (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
      (HOLD ena (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_counter_1m\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (460:460:460) (460:460:460))
        (PORT datab (307:307:307) (307:307:307))
        (PORT datac (434:434:434) (434:434:434))
        (PORT datad (438:438:438) (438:438:438))
        (IOPATH dataa regin (568:568:568) (568:568:568))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_counter_1m\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (802:802:802) (802:802:802))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_counter_1m\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (691:691:691) (691:691:691))
        (PORT clk (3964:3964:3964) (3964:3964:3964))
        (PORT ena (1579:1579:1579) (1579:1579:1579))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (SETUP ena (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
      (HOLD ena (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\process4\~39_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (439:439:439) (439:439:439))
        (PORT datab (560:560:560) (560:560:560))
        (PORT datad (841:841:841) (841:841:841))
        (IOPATH dataa combout (454:454:454) (454:454:454))
        (IOPATH datab combout (340:340:340) (340:340:340))
        (IOPATH datad combout (88:88:88) (88:88:88))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Equal6\~38_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (446:446:446) (446:446:446))
        (PORT datad (475:475:475) (475:475:475))
        (IOPATH datac combout (225:225:225) (225:225:225))
        (IOPATH datad combout (88:88:88) (88:88:88))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Equal0\~38_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (467:467:467) (467:467:467))
        (PORT datad (465:465:465) (465:465:465))
        (IOPATH datac combout (225:225:225) (225:225:225))
        (IOPATH datad combout (88:88:88) (88:88:88))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Equal4\~38_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (444:444:444) (444:444:444))
        (PORT datad (453:453:453) (453:453:453))
        (IOPATH datac combout (225:225:225) (225:225:225))
        (IOPATH datad combout (88:88:88) (88:88:88))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Equal2\~38_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (417:417:417) (417:417:417))
        (PORT datac (467:467:467) (467:467:467))
        (IOPATH datab combout (340:340:340) (340:340:340))
        (IOPATH datac combout (225:225:225) (225:225:225))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\sel_temp\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (457:457:457) (457:457:457))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\sel_temp\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (691:691:691) (691:691:691))
        (PORT clk (1009:1009:1009) (1009:1009:1009))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\sel_temp\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (468:468:468) (468:468:468))
        (PORT datad (458:458:458) (458:458:458))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\sel_temp\[1\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (836:836:836) (836:836:836))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\sel_temp\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (691:691:691) (691:691:691))
        (PORT clk (1009:1009:1009) (1009:1009:1009))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\sel_temp\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (443:443:443) (443:443:443))
        (PORT datac (463:463:463) (463:463:463))
        (PORT datad (457:457:457) (457:457:457))
        (IOPATH datab regin (467:467:467) (467:467:467))
        (IOPATH datad regin (238:238:238) (238:238:238))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\sel_temp\[2\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (831:831:831) (831:831:831))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\sel_temp\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (691:691:691) (691:691:691))
        (PORT clk (1009:1009:1009) (1009:1009:1009))
        (IOPATH (posedge clk) regout (173:173:173) (173:173:173))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (29:29:29))
      (HOLD datain (posedge clk) (12:12:12))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Mux4\~24_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (445:445:445) (445:445:445))
        (PORT datac (463:463:463) (463:463:463))
        (PORT datad (457:457:457) (457:457:457))
        (IOPATH datab combout (340:340:340) (340:340:340))
        (IOPATH datac combout (225:225:225) (225:225:225))
        (IOPATH datad combout (88:88:88) (88:88:88))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\reset\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1130:1130:1130) (1130:1130:1130))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\clk_10s\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (465:465:465) (465:465:465))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\clk_10s\[0\]\~I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (833:833:833) (833:833:833))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\clk_10s\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1158:1158:1158) (1158:1158:1158))