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📄 clock.vho

📁 基于SMART-I实验平台的时钟电路设计与实现
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	clk => \clk~combout\,
	dataa => \clk_1s[3]\,
	datab => \clk_1s[1]\,
	datac => \clk_1s[2]\,
	datad => \clk_1s[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1s[3]~I_modesel\,
	regout => \clk_1s[3]\);

-- atom is at LC_X24_Y9_N1
\Mux0~122_I\ : cyclone_lcell
-- Equation(s):
-- \Mux0~122\ = \sel_temp[2]\ & (\sel_temp[0]\) # !\sel_temp[2]\ & (\sel_temp[0]\ & \clk_10s[3]\ # !\sel_temp[0]\ & (\clk_1s[3]\))

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "EE30",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \Mux0~122_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \clk_10s[3]\,
	datab => \sel_temp[2]\,
	datac => \clk_1s[3]\,
	datad => \sel_temp[0]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Mux0~122_I_modesel\,
	combout => \Mux0~122\);

-- atom is at LC_X26_Y13_N9
\clk_1h[0]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[0]\ = DFFEAS(!\clk_1h[0]\, GLOBAL(clk_counter_1h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0F0F",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1h[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_1h,
	dataa => VCC,
	datab => VCC,
	datac => \clk_1h[0]\,
	datad => VCC,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1h[0]~I_modesel\,
	regout => \clk_1h[0]\);

-- atom is at LC_X25_Y13_N5
\clk_10h[0]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10h[0]\ = DFFEAS(!\clk_10h[0]\ & (\clk_10h[3]\ # \clk_10h[2]\ # !\clk_10h[1]\), GLOBAL(clk_counter_10h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "3233",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10h[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10h,
	dataa => \clk_10h[3]\,
	datab => \clk_10h[0]\,
	datac => \clk_10h[2]\,
	datad => \clk_10h[1]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10h[0]~I_modesel\,
	regout => \clk_10h[0]\);

-- atom is at LC_X25_Y13_N9
\clk_10h[3]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10h[3]\ = DFFEAS(\clk_10h[3]\ $ (\clk_10h[0]\ & \clk_10h[2]\ & \clk_10h[1]\), GLOBAL(clk_counter_10h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "6AAA",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10h[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10h,
	dataa => \clk_10h[3]\,
	datab => \clk_10h[0]\,
	datac => \clk_10h[2]\,
	datad => \clk_10h[1]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10h[3]~I_modesel\,
	regout => \clk_10h[3]\);

-- atom is at LC_X25_Y13_N7
\clk_10h[1]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10h[1]\ = DFFEAS(\clk_10h[0]\ & (!\clk_10h[1]\) # !\clk_10h[0]\ & \clk_10h[1]\ & (\clk_10h[3]\ # \clk_10h[2]\), GLOBAL(clk_counter_10h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "32CC",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10h[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10h,
	dataa => \clk_10h[3]\,
	datab => \clk_10h[0]\,
	datac => \clk_10h[2]\,
	datad => \clk_10h[1]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10h[1]~I_modesel\,
	regout => \clk_10h[1]\);

-- atom is at LC_X25_Y13_N8
\clk_10h[2]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10h[2]\ = DFFEAS(\clk_10h[2]\ $ (\clk_10h[1]\ & \clk_10h[0]\), GLOBAL(clk_counter_10h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "7878",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10h[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10h,
	dataa => \clk_10h[1]\,
	datab => \clk_10h[0]\,
	datac => \clk_10h[2]\,
	datad => VCC,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10h[2]~I_modesel\,
	regout => \clk_10h[2]\);

-- atom is at LC_X25_Y13_N3
\clk_1h[1]~208_I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[1]~208\ = \clk_1h[3]\ & !\clk_1h[1]\ & !\clk_10h[1]\ # !\clk_1h[3]\ & \clk_1h[1]\ & \clk_10h[1]\ & !\clk_10h[0]\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0242",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1h[1]~208_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \clk_1h[3]\,
	datab => \clk_1h[1]\,
	datac => \clk_10h[1]\,
	datad => \clk_10h[0]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1h[1]~208_I_modesel\,
	combout => \clk_1h[1]~208\);

-- atom is at LC_X25_Y13_N0
\clk_1h[1]~206_I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[1]~206\ = !\clk_10h[3]\ & \clk_1h[1]~208\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0F00",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1h[1]~206_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => VCC,
	datac => \clk_10h[3]\,
	datad => \clk_1h[1]~208\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1h[1]~206_I_modesel\,
	combout => \clk_1h[1]~206\);

-- atom is at LC_X25_Y13_N1
\clk_1h[1]~216_I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[1]~216\ = !\clk_1h[2]\ & \clk_1h[0]\ & !\clk_10h[2]\ & \clk_1h[1]~206\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0400",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1h[1]~216_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \clk_1h[2]\,
	datab => \clk_1h[0]\,
	datac => \clk_10h[2]\,
	datad => \clk_1h[1]~206\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1h[1]~216_I_modesel\,
	combout => \clk_1h[1]~216\);

-- atom is at LC_X25_Y13_N4
\clk_1h[1]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[1]\ = DFFEAS(!\clk_1h[1]~216\ & (\clk_1h[0]\ $ \clk_1h[1]\), GLOBAL(clk_counter_1h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "003C",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1h[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_1h,
	dataa => VCC,
	datab => \clk_1h[0]\,
	datac => \clk_1h[1]\,
	datad => \clk_1h[1]~216\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1h[1]~I_modesel\,
	regout => \clk_1h[1]\);

-- atom is at LC_X25_Y13_N6
\clk_1h[2]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[2]\ = DFFEAS(!\clk_1h[1]~216\ & (\clk_1h[2]\ $ (\clk_1h[0]\ & \clk_1h[1]\)), GLOBAL(clk_counter_1h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "006A",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1h[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_1h,
	dataa => \clk_1h[2]\,
	datab => \clk_1h[0]\,
	datac => \clk_1h[1]\,
	datad => \clk_1h[1]~216\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1h[2]~I_modesel\,
	regout => \clk_1h[2]\);

-- atom is at LC_X26_Y13_N4
\Add4~103_I\ : cyclone_lcell
-- Equation(s):
-- \Add4~103\ = \clk_1h[0]\ & (\clk_1h[1]\)

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "A0A0",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \Add4~103_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \clk_1h[0]\,
	datab => VCC,
	datac => \clk_1h[1]\,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Add4~103_I_modesel\,
	combout => \Add4~103\);

-- atom is at LC_X25_Y13_N2
\clk_1h[3]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[3]\ = DFFEAS(!\clk_1h[1]~216\ & (\clk_1h[3]\ $ (\clk_1h[2]\ & \Add4~103\)), GLOBAL(clk_counter_1h), GLOBAL(\reset~combout\), , , , , , )
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