clock.vho

基于SMART-I实验平台的时钟电路设计与实现

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

-- DATE "11/04/2006 14:20:49"

-- 
-- Device: Altera EP1C3T144C6 Package TQFP144
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	clock IS
    PORT (
	clk : IN std_logic;
	reset : IN std_logic;
	LEDOUT : OUT std_logic_vector(7 DOWNTO 0);
	sel : OUT std_logic_vector(2 DOWNTO 0)
	);
END clock;

ARCHITECTURE structure OF clock IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_LEDOUT : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_sel : std_logic_vector(2 DOWNTO 0);
SIGNAL \clk~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \clk_counter_1h~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_counter_1h~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_counter_10s~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_counter_10s~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_counter_10h~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_counter_10h~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_counter_10m~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_counter_10m~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_counter_1m~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_counter_1m~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process4~39_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process4~39_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Equal6~38_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Equal6~38_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Equal0~38_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Equal0~38_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Equal4~38_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Equal4~38_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Equal2~38_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Equal2~38_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sel_temp[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \sel_temp[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sel_temp[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \sel_temp[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sel_temp[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \sel_temp[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux4~24_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux4~24_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \reset~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \clk_10s[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10s[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10s[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10s[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10s[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10s[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10s[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10s[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1s[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1s[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1s[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1s[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1s[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1s[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1s[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1s[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux0~122_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux0~122_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1h[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1h[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10h[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10h[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10h[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10h[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10h[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10h[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10h[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10h[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1h[1]~208_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1h[1]~208_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1h[1]~206_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1h[1]~206_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1h[1]~216_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1h[1]~216_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1h[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1h[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1h[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1h[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Add4~103_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Add4~103_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1h[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1h[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux0~123_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux0~123_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1m[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1m[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1m[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1m[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1m[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1m[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_1m[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_1m[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10m[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10m[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10m[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10m[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10m[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10m[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk_10m[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clk_10m[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux0~124_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux0~124_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux0~125_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux0~125_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux3~150_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux3~150_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux3~148_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux3~148_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux3~149_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux3~149_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux3~151_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux3~151_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux1~124_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux1~124_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux1~125_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux1~125_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux1~126_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux1~126_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux1~127_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux1~127_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux2~140_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux2~140_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux2~141_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux2~141_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux2~142_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux2~142_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux2~143_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux2~143_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux11~30_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux11~30_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux10~29_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux10~29_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux9~77_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux9~77_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux8~31_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux8~31_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux7~49_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux7~49_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux6~128_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux6~128_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Mux5~33_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Mux5~33_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \LEDOUT[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \LEDOUT[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \LEDOUT[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \LEDOUT[3]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \LEDOUT[4]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \LEDOUT[5]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \LEDOUT[6]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \LEDOUT[7]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \sel[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \sel[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \sel[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL clk_counter_1h : std_logic;
SIGNAL clk_counter_10s : std_logic;
SIGNAL clk_counter_10h : std_logic;
SIGNAL clk_counter_10m : std_logic;
SIGNAL clk_counter_1m : std_logic;
SIGNAL \process4~39\ : std_logic;
SIGNAL \Equal6~38\ : std_logic;
SIGNAL \Equal0~38\ : std_logic;
SIGNAL \Equal4~38\ : std_logic;
SIGNAL \Equal2~38\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \sel_temp[0]\ : std_logic;
SIGNAL \sel_temp[1]\ : std_logic;
SIGNAL \sel_temp[2]\ : std_logic;
SIGNAL \Mux4~24\ : std_logic;
SIGNAL \reset~combout\ : std_logic;
SIGNAL \clk_10s[0]\ : std_logic;
SIGNAL \clk_10s[2]\ : std_logic;
SIGNAL \clk_10s[1]\ : std_logic;
SIGNAL \clk_10s[3]\ : std_logic;
SIGNAL \clk_1s[0]\ : std_logic;
SIGNAL \clk_1s[2]\ : std_logic;
SIGNAL \clk_1s[1]\ : std_logic;
SIGNAL \clk_1s[3]\ : std_logic;
SIGNAL \Mux0~122\ : std_logic;
SIGNAL \clk_1h[0]\ : std_logic;
SIGNAL \clk_10h[0]\ : std_logic;
SIGNAL \clk_10h[3]\ : std_logic;
SIGNAL \clk_10h[1]\ : std_logic;
SIGNAL \clk_10h[2]\ : std_logic;
SIGNAL \clk_1h[1]~208\ : std_logic;
SIGNAL \clk_1h[1]~206\ : std_logic;
SIGNAL \clk_1h[1]~216\ : std_logic;
SIGNAL \clk_1h[1]\ : std_logic;
SIGNAL \clk_1h[2]\ : std_logic;
SIGNAL \Add4~103\ : std_logic;
SIGNAL \clk_1h[3]\ : std_logic;
SIGNAL \Mux0~123\ : std_logic;
SIGNAL \clk_1m[0]\ : std_logic;
SIGNAL \clk_1m[1]\ : std_logic;
SIGNAL \clk_1m[2]\ : std_logic;
SIGNAL \clk_1m[3]\ : std_logic;
SIGNAL \clk_10m[0]\ : std_logic;
SIGNAL \clk_10m[2]\ : std_logic;
SIGNAL \clk_10m[1]\ : std_logic;
SIGNAL \clk_10m[3]\ : std_logic;
SIGNAL \Mux0~124\ : std_logic;
SIGNAL \Mux0~125\ : std_logic;
SIGNAL \Mux3~150\ : std_logic;
SIGNAL \Mux3~148\ : std_logic;
SIGNAL \Mux3~149\ : std_logic;
SIGNAL \Mux3~151\ : std_logic;
SIGNAL \Mux1~124\ : std_logic;
SIGNAL \Mux1~125\ : std_logic;
SIGNAL \Mux1~126\ : std_logic;
SIGNAL \Mux1~127\ : std_logic;
SIGNAL \Mux2~140\ : std_logic;
SIGNAL \Mux2~141\ : std_logic;
SIGNAL \Mux2~142\ : std_logic;
SIGNAL \Mux2~143\ : std_logic;
SIGNAL \Mux11~30\ : std_logic;
SIGNAL \Mux10~29\ : std_logic;
SIGNAL \Mux9~77\ : std_logic;
SIGNAL \Mux8~31\ : std_logic;
SIGNAL \Mux7~49\ : std_logic;
SIGNAL \Mux6~128\ : std_logic;
SIGNAL \Mux5~33\ : std_logic;
SIGNAL \ALT_INV_Mux10~29\ : std_logic;
SIGNAL \ALT_INV_Mux9~77\ : std_logic;
SIGNAL \ALT_INV_Mux8~31\ : std_logic;
SIGNAL \ALT_INV_Mux7~49\ : std_logic;
SIGNAL \ALT_INV_Mux5~33\ : std_logic;
SIGNAL \ALT_INV_reset~combout\ : std_logic;
COMPONENT cyclone_lcell
PORT (
	clk : IN STD_LOGIC;
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cin0 : IN STD_LOGIC;
	cin1 : IN STD_LOGIC;
	inverta : IN STD_LOGIC;
	regcascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cout0 : OUT STD_LOGIC;
	cout1 : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	enable_asynch_arcs : IN STD_LOGIC);
END COMPONENT;

COMPONENT cyclone_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(26 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_clk <= clk;
ww_reset <= reset;
LEDOUT <= ww_LEDOUT;
sel <= ww_sel;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\clk~I_modesel\ <= "000000000000000000000000001";
\clk_counter_1h~I_modesel\ <= "1100001010101";
\clk_counter_1h~I_pathsel\ <= "00000001111";
\clk_counter_10s~I_modesel\ <= "1100001010101";
\clk_counter_10s~I_pathsel\ <= "00000001111";
\clk_counter_10h~I_modesel\ <= "1100001010101";
\clk_counter_10h~I_pathsel\ <= "00000001111";
\clk_counter_10m~I_modesel\ <= "1100001010101";
\clk_counter_10m~I_pathsel\ <= "00000001111";
\clk_counter_1m~I_modesel\ <= "1100001010101";
\clk_counter_1m~I_pathsel\ <= "00000001111";
\process4~39_I_modesel\ <= "1001001010101";
\process4~39_I_pathsel\ <= "00000001011";
\Equal6~38_I_modesel\ <= "1001001010101";
\Equal6~38_I_pathsel\ <= "00000001100";
\Equal0~38_I_modesel\ <= "1001001010101";
\Equal0~38_I_pathsel\ <= "00000001100";
\Equal4~38_I_modesel\ <= "1001001010101";
\Equal4~38_I_pathsel\ <= "00000001100";
\Equal2~38_I_modesel\ <= "1001001010101";
\Equal2~38_I_pathsel\ <= "00000000110";
\sel_temp[0]~I_modesel\ <= "1100001010101";
\sel_temp[0]~I_pathsel\ <= "00000001000";
\sel_temp[1]~I_modesel\ <= "1100001010101";
\sel_temp[1]~I_pathsel\ <= "00000001100";
\sel_temp[2]~I_modesel\ <= "1100001010101";
\sel_temp[2]~I_pathsel\ <= "00000001110";
\Mux4~24_I_modesel\ <= "1001001010101";
\Mux4~24_I_pathsel\ <= "00000001110";
\reset~I_modesel\ <= "000000000000000000000000001";
\clk_10s[0]~I_modesel\ <= "1100001010101";
\clk_10s[0]~I_pathsel\ <= "00000000100";
\clk_10s[2]~I_modesel\ <= "1100001010101";
\clk_10s[2]~I_pathsel\ <= "00000001111";
\clk_10s[1]~I_modesel\ <= "1100001010101";
\clk_10s[1]~I_pathsel\ <= "00000001111";
\clk_10s[3]~I_modesel\ <= "1100001010101";
\clk_10s[3]~I_pathsel\ <= "00000001111";
\clk_1s[0]~I_modesel\ <= "1100001010101";
\clk_1s[0]~I_pathsel\ <= "00000001000";
\clk_1s[2]~I_modesel\ <= "1100001010101";
\clk_1s[2]~I_pathsel\ <= "00000001110";
\clk_1s[1]~I_modesel\ <= "1100001010101";
\clk_1s[1]~I_pathsel\ <= "00000001111";
\clk_1s[3]~I_modesel\ <= "1100001010101";
\clk_1s[3]~I_pathsel\ <= "00000001111";
\Mux0~122_I_modesel\ <= "1001001010101";
\Mux0~122_I_pathsel\ <= "00000001111";
\clk_1h[0]~I_modesel\ <= "1100001010101";
\clk_1h[0]~I_pathsel\ <= "00000000100";
\clk_10h[0]~I_modesel\ <= "1100001010101";
\clk_10h[0]~I_pathsel\ <= "00000001111";
\clk_10h[3]~I_modesel\ <= "1100001010101";
\clk_10h[3]~I_pathsel\ <= "00000001111";
\clk_10h[1]~I_modesel\ <= "1100001010101";
\clk_10h[1]~I_pathsel\ <= "00000001111";
\clk_10h[2]~I_modesel\ <= "1100001010101";
\clk_10h[2]~I_pathsel\ <= "00000000111";
\clk_1h[1]~208_I_modesel\ <= "1001001010101";
\clk_1h[1]~208_I_pathsel\ <= "00000001111";
\clk_1h[1]~206_I_modesel\ <= "1001001010101";
\clk_1h[1]~206_I_pathsel\ <= "00000001100";
\clk_1h[1]~216_I_modesel\ <= "1001001010101";
\clk_1h[1]~216_I_pathsel\ <= "00000001111";
\clk_1h[1]~I_modesel\ <= "1100001010101";
\clk_1h[1]~I_pathsel\ <= "00000001110";
\clk_1h[2]~I_modesel\ <= "1100001010101";
\clk_1h[2]~I_pathsel\ <= "00000001111";
\Add4~103_I_modesel\ <= "1001001010101";
\Add4~103_I_pathsel\ <= "00000000101";
\clk_1h[3]~I_modesel\ <= "1100001010101";
\clk_1h[3]~I_pathsel\ <= "00000001111";
\Mux0~123_I_modesel\ <= "1001001010101";
\Mux0~123_I_pathsel\ <= "00000001111";
\clk_1m[0]~I_modesel\ <= "1100001010101";
\clk_1m[0]~I_pathsel\ <= "00000001000";
\clk_1m[1]~I_modesel\ <= "1100001010101";
\clk_1m[1]~I_pathsel\ <= "00000001111";
\clk_1m[2]~I_modesel\ <= "1100001010101";
\clk_1m[2]~I_pathsel\ <= "00000001110";
\clk_1m[3]~I_modesel\ <= "1100001010101";
\clk_1m[3]~I_pathsel\ <= "00000001111";
\clk_10m[0]~I_modesel\ <= "1100001010101";
\clk_10m[0]~I_pathsel\ <= "00000001000";
\clk_10m[2]~I_modesel\ <= "1100001010101";
\clk_10m[2]~I_pathsel\ <= "00000001111";
\clk_10m[1]~I_modesel\ <= "1100001010101";
\clk_10m[1]~I_pathsel\ <= "00000001111";
\clk_10m[3]~I_modesel\ <= "1100001010101";
\clk_10m[3]~I_pathsel\ <= "00000001111";
\Mux0~124_I_modesel\ <= "1001001010101";
\Mux0~124_I_pathsel\ <= "00000000111";
\Mux0~125_I_modesel\ <= "1001001010101";
\Mux0~125_I_pathsel\ <= "00000001111";
\Mux3~150_I_modesel\ <= "1001001010101";
\Mux3~150_I_pathsel\ <= "00000000111";
\Mux3~148_I_modesel\ <= "1001001010101";
\Mux3~148_I_pathsel\ <= "00000001111";
\Mux3~149_I_modesel\ <= "1001001010101";
\Mux3~149_I_pathsel\ <= "00000001111";
\Mux3~151_I_modesel\ <= "1001001010101";
\Mux3~151_I_pathsel\ <= "00000001111";
\Mux1~124_I_modesel\ <= "1001001010101";
\Mux1~124_I_pathsel\ <= "00000001111";
\Mux1~125_I_modesel\ <= "1001001010101";
\Mux1~125_I_pathsel\ <= "00000001111";
\Mux1~126_I_modesel\ <= "1001001010101";
\Mux1~126_I_pathsel\ <= "00000000111";
\Mux1~127_I_modesel\ <= "1001001010101";