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📄 clock.vho

📁 基于SMART-I实验平台的时钟电路设计与实现
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1234 
	combout => \Mux2~141\);

\Mux2~142_I\ : cyclone_lcell
-- Equation(s):
-- \Mux2~142\ = sel_temp(0) & clk_10m(1) # !sel_temp(0) & (clk_1m(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "ACAC",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_10m(1),
	datab => clk_1m(1),
	datac => sel_temp(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux2~142\);

\Mux2~143_I\ : cyclone_lcell
-- Equation(s):
-- \Mux2~143\ = sel_temp(1) & !sel_temp(2) & (\Mux2~142\) # !sel_temp(1) & (\Mux2~141\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "50CC",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => sel_temp(2),
	datab => \Mux2~141\,
	datac => \Mux2~142\,
	datad => sel_temp(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux2~143\);

\Mux11~30_I\ : cyclone_lcell
-- Equation(s):
-- \Mux11~30\ = \Mux0~125\ # \Mux1~127\ & (!\Mux2~143\ # !\Mux3~151\) # !\Mux1~127\ & (\Mux2~143\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "BFFA",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Mux0~125\,
	datab => \Mux3~151\,
	datac => \Mux1~127\,
	datad => \Mux2~143\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux11~30\);

\Mux10~29_I\ : cyclone_lcell
-- Equation(s):
-- \Mux10~29\ = !\Mux0~125\ & (\Mux3~151\ & (\Mux2~143\ # !\Mux1~127\) # !\Mux3~151\ & !\Mux1~127\ & \Mux2~143\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "4504",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Mux0~125\,
	datab => \Mux3~151\,
	datac => \Mux1~127\,
	datad => \Mux2~143\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux10~29\);

\Mux9~77_I\ : cyclone_lcell
-- Equation(s):
-- \Mux9~77\ = \Mux3~151\ # \Mux1~127\ & !\Mux2~143\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "CCFC",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => \Mux3~151\,
	datac => \Mux1~127\,
	datad => \Mux2~143\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux9~77\);

\Mux8~31_I\ : cyclone_lcell
-- Equation(s):
-- \Mux8~31\ = !\Mux0~125\ & (\Mux3~151\ & (\Mux1~127\ $ !\Mux2~143\) # !\Mux3~151\ & \Mux1~127\ & !\Mux2~143\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "4014",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Mux0~125\,
	datab => \Mux3~151\,
	datac => \Mux1~127\,
	datad => \Mux2~143\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux8~31\);

\Mux7~49_I\ : cyclone_lcell
-- Equation(s):
-- \Mux7~49\ = !\Mux3~151\ & !\Mux1~127\ & \Mux2~143\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0300",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => \Mux3~151\,
	datac => \Mux1~127\,
	datad => \Mux2~143\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux7~49\);

\Mux6~128_I\ : cyclone_lcell
-- Equation(s):
-- \Mux6~128\ = \Mux3~151\ $ !\Mux2~143\ # !\Mux1~127\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "CF3F",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => \Mux3~151\,
	datac => \Mux1~127\,
	datad => \Mux2~143\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux6~128\);

\Mux5~33_I\ : cyclone_lcell
-- Equation(s):
-- \Mux5~33\ = !\Mux0~125\ & !\Mux2~143\ & (\Mux3~151\ $ \Mux1~127\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0014",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Mux0~125\,
	datab => \Mux3~151\,
	datac => \Mux1~127\,
	datad => \Mux2~143\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux5~33\);

\LEDOUT[0]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \Mux4~24\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDOUT(0));

\LEDOUT[1]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \Mux11~30\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDOUT(1));

\LEDOUT[2]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux10~29\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDOUT(2));

\LEDOUT[3]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux9~77\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDOUT(3));

\LEDOUT[4]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux8~31\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDOUT(4));

\LEDOUT[5]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux7~49\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDOUT(5));

\LEDOUT[6]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \Mux6~128\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDOUT(6));

\LEDOUT[7]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_Mux5~33\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_LEDOUT(7));

\sel[0]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => sel_temp(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_sel(0));

\sel[1]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => sel_temp(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_sel(1));

\sel[2]~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => sel_temp(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_sel(2));
END structure;
1234

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