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📄 clock.vho

📁 基于SMART-I实验平台的时钟电路设计与实现
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PORT MAP (
	clk => clk_counter_1h,
	dataa => clk_1h(2),
	datab => \Add4~103\,
	datac => clk_1h(3),
	datad => \clk_1h[1]~216\,
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1h(3));

\Mux0~123_I\ : cyclone_lcell
-- Equation(s):
-- \Mux0~123\ = \Mux0~122\ & (clk_10h(3) # !sel_temp(2)) # !\Mux0~122\ & sel_temp(2) & clk_1h(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "EA62",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Mux0~122\,
	datab => sel_temp(2),
	datac => clk_1h(3),
	datad => clk_10h(3),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux0~123\);

\clk_1m[0]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1m(0) = DFFEAS(!clk_1m(0), GLOBAL(clk_counter_1m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1m,
	datad => clk_1m(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1m(0));

\clk_1m[1]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1m(1) = DFFEAS(clk_1m(1) & (!clk_1m(0)) # !clk_1m(1) & clk_1m(0) & (clk_1m(2) # !clk_1m(3)), GLOBAL(clk_counter_1m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0DF0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1m,
	dataa => clk_1m(3),
	datab => clk_1m(2),
	datac => clk_1m(1),
	datad => clk_1m(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1m(1));

\clk_1m[2]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1m(2) = DFFEAS(clk_1m(2) $ (clk_1m(1) & clk_1m(0)), GLOBAL(clk_counter_1m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3CCC",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1m,
	datab => clk_1m(2),
	datac => clk_1m(1),
	datad => clk_1m(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1m(2));

\clk_1m[3]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1m(3) = DFFEAS(clk_1m(3) & (clk_1m(2) $ clk_1m(1) # !clk_1m(0)) # !clk_1m(3) & clk_1m(2) & clk_1m(1) & clk_1m(0), GLOBAL(clk_counter_1m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "68AA",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1m,
	dataa => clk_1m(3),
	datab => clk_1m(2),
	datac => clk_1m(1),
	datad => clk_1m(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1m(3));

\clk_10m[0]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10m(0) = DFFEAS(!clk_10m(0), GLOBAL(clk_counter_10m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10m,
	datad => clk_10m(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10m(0));

\clk_10m[2]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10m(2) = DFFEAS(clk_10m(1) & (clk_10m(2) $ clk_10m(0)) # !clk_10m(1) & clk_10m(2) & (clk_10m(3) # !clk_10m(0)), GLOBAL(clk_counter_10m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "4AF0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10m,
	dataa => clk_10m(1),
	datab => clk_10m(3),
	datac => clk_10m(2),
	datad => clk_10m(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10m(2));

\clk_10m[1]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10m(1) = DFFEAS(clk_10m(1) & (!clk_10m(0)) # !clk_10m(1) & clk_10m(0) & (clk_10m(3) # !clk_10m(2)), GLOBAL(clk_counter_10m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "45AA",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10m,
	dataa => clk_10m(1),
	datab => clk_10m(3),
	datac => clk_10m(2),
	datad => clk_10m(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10m(1));

\clk_10m[3]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10m(3) = DFFEAS(clk_10m(3) $ (clk_10m(1) & clk_10m(2) & clk_10m(0)), GLOBAL(clk_counter_10m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "6CCC",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10m,
	dataa => clk_10m(1),
	datab => clk_10m(3),
	datac => clk_10m(2),
	datad => clk_10m(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10m(3));

\Mux0~124_I\ : cyclone_lcell
-- Equation(s):
-- \Mux0~124\ = sel_temp(0) & (clk_10m(3)) # !sel_temp(0) & clk_1m(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "CACA",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1m(3),
	datab => clk_10m(3),
	datac => sel_temp(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux0~124\);

\Mux0~125_I\ : cyclone_lcell
-- Equation(s):
-- \Mux0~125\ = sel_temp(1) & (!sel_temp(2) & \Mux0~124\) # !sel_temp(1) & \Mux0~123\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3A0A",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Mux0~123\,
	datab => sel_temp(2),
	datac => sel_temp(1),
	datad => \Mux0~124\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux0~125\);

\Mux3~150_I\ : cyclone_lcell
-- Equation(s):
-- \Mux3~150\ = sel_temp(0) & (clk_10m(0)) # !sel_temp(0) & clk_1m(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "CACA",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1m(0),
	datab => clk_10m(0),
	datac => sel_temp(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux3~150\);

\Mux3~148_I\ : cyclone_lcell
-- Equation(s):
-- \Mux3~148\ = sel_temp(2) & sel_temp(0) # !sel_temp(2) & (sel_temp(0) & (clk_10s(0)) # !sel_temp(0) & clk_1s(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "DC98",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => sel_temp(2),
	datab => sel_temp(0),
	datac => clk_1s(0),
	datad => clk_10s(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux3~148\);

\Mux3~149_I\ : cyclone_lcell
-- Equation(s):
-- \Mux3~149\ = sel_temp(2) & (\Mux3~148\ & (clk_10h(0)) # !\Mux3~148\ & clk_1h(0)) # !sel_temp(2) & (\Mux3~148\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "CFA0",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1h(0),
	datab => clk_10h(0),
	datac => sel_temp(2),
	datad => \Mux3~148\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux3~149\);

\Mux3~151_I\ : cyclone_lcell
-- Equation(s):
-- \Mux3~151\ = sel_temp(1) & \Mux3~150\ & !sel_temp(2) # !sel_temp(1) & (\Mux3~149\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3B08",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Mux3~150\,
	datab => sel_temp(1),
	datac => sel_temp(2),
	datad => \Mux3~149\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux3~151\);

\Mux1~124_I\ : cyclone_lcell
-- Equation(s):
-- \Mux1~124\ = sel_temp(2) & (sel_temp(0)) # !sel_temp(2) & (sel_temp(0) & clk_10s(2) # !sel_temp(0) & (clk_1s(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "EE50",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => sel_temp(2),
	datab => clk_10s(2),
	datac => clk_1s(2),
	datad => sel_temp(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux1~124\);

\Mux1~125_I\ : cyclone_lcell
-- Equation(s):
-- \Mux1~125\ = sel_temp(2) & (\Mux1~124\ & (clk_10h(2)) # !\Mux1~124\ & clk_1h(2)) # !sel_temp(2) & \Mux1~124\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "EC64",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => sel_temp(2),
	datab => \Mux1~124\,
	datac => clk_1h(2),
	datad => clk_10h(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux1~125\);

\Mux1~126_I\ : cyclone_lcell
-- Equation(s):
-- \Mux1~126\ = sel_temp(0) & (clk_10m(2)) # !sel_temp(0) & clk_1m(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "CACA",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1m(2),
	datab => clk_10m(2),
	datac => sel_temp(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux1~126\);

\Mux1~127_I\ : cyclone_lcell
-- Equation(s):
-- \Mux1~127\ = sel_temp(1) & (!sel_temp(2) & \Mux1~126\) # !sel_temp(1) & \Mux1~125\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3A0A",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Mux1~125\,
	datab => sel_temp(2),
	datac => sel_temp(1),
	datad => \Mux1~126\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux1~127\);

\Mux2~140_I\ : cyclone_lcell
-- Equation(s):
-- \Mux2~140\ = sel_temp(0) & (sel_temp(2)) # !sel_temp(0) & (sel_temp(2) & (clk_1h(1)) # !sel_temp(2) & clk_1s(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "F2C2",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1s(1),
	datab => sel_temp(0),
	datac => sel_temp(2),
	datad => clk_1h(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux2~140\);

\Mux2~141_I\ : cyclone_lcell
-- Equation(s):
-- \Mux2~141\ = \Mux2~140\ & (clk_10h(1) # !sel_temp(0)) # !\Mux2~140\ & clk_10s(1) & sel_temp(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "EC2C",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_10s(1),
	datab => \Mux2~140\,
	datac => sel_temp(0),
	datad => clk_10h(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
1234

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