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📄 clock.vho

📁 基于SMART-I实验平台的时钟电路设计与实现
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	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_reset,
	combout => \reset~combout\);

\clk_10s[0]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10s(0) = DFFEAS(!clk_10s(0), GLOBAL(clk_counter_10s), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0F0F",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10s,
	datac => clk_10s(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10s(0));

\clk_10s[2]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10s(2) = DFFEAS(clk_10s(0) & (clk_10s(1) & (!clk_10s(2)) # !clk_10s(1) & clk_10s(3) & clk_10s(2)) # !clk_10s(0) & (clk_10s(2)), GLOBAL(clk_counter_10s), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "7588",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10s,
	dataa => clk_10s(0),
	datab => clk_10s(1),
	datac => clk_10s(3),
	datad => clk_10s(2),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10s(2));

\clk_10s[1]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10s(1) = DFFEAS(clk_10s(0) & !clk_10s(1) & (clk_10s(3) # !clk_10s(2)) # !clk_10s(0) & clk_10s(1), GLOBAL(clk_counter_10s), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "6466",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10s,
	dataa => clk_10s(0),
	datab => clk_10s(1),
	datac => clk_10s(3),
	datad => clk_10s(2),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10s(1));

\clk_10s[3]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10s(3) = DFFEAS(clk_10s(3) $ (clk_10s(0) & clk_10s(1) & clk_10s(2)), GLOBAL(clk_counter_10s), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "78F0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10s,
	dataa => clk_10s(0),
	datab => clk_10s(1),
	datac => clk_10s(3),
	datad => clk_10s(2),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10s(3));

\clk_1s[0]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1s(0) = DFFEAS(!clk_1s(0), GLOBAL(\clk~combout\), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datad => clk_1s(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1s(0));

\clk_1s[2]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1s(2) = DFFEAS(clk_1s(2) $ (clk_1s(1) & clk_1s(0)), GLOBAL(\clk~combout\), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3CF0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => clk_1s(1),
	datac => clk_1s(2),
	datad => clk_1s(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1s(2));

\clk_1s[1]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1s(1) = DFFEAS(clk_1s(1) & (!clk_1s(0)) # !clk_1s(1) & clk_1s(0) & (clk_1s(2) # !clk_1s(3)), GLOBAL(\clk~combout\), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "31CC",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => clk_1s(3),
	datab => clk_1s(1),
	datac => clk_1s(2),
	datad => clk_1s(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1s(1));

\clk_1s[3]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1s(3) = DFFEAS(clk_1s(3) & (clk_1s(1) $ clk_1s(2) # !clk_1s(0)) # !clk_1s(3) & clk_1s(1) & clk_1s(2) & clk_1s(0), GLOBAL(\clk~combout\), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "68AA",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => clk_1s(3),
	datab => clk_1s(1),
	datac => clk_1s(2),
	datad => clk_1s(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1s(3));

\Mux0~122_I\ : cyclone_lcell
-- Equation(s):
-- \Mux0~122\ = sel_temp(2) & (sel_temp(0)) # !sel_temp(2) & (sel_temp(0) & clk_10s(3) # !sel_temp(0) & (clk_1s(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "EE30",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_10s(3),
	datab => sel_temp(2),
	datac => clk_1s(3),
	datad => sel_temp(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux0~122\);

\clk_1h[0]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1h(0) = DFFEAS(!clk_1h(0), GLOBAL(clk_counter_1h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0F0F",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1h,
	datac => clk_1h(0),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1h(0));

\clk_10h[0]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10h(0) = DFFEAS(!clk_10h(0) & (clk_10h(3) # clk_10h(2) # !clk_10h(1)), GLOBAL(clk_counter_10h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3233",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10h,
	dataa => clk_10h(3),
	datab => clk_10h(0),
	datac => clk_10h(2),
	datad => clk_10h(1),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10h(0));

\clk_10h[3]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10h(3) = DFFEAS(clk_10h(3) $ (clk_10h(0) & clk_10h(2) & clk_10h(1)), GLOBAL(clk_counter_10h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "6AAA",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10h,
	dataa => clk_10h(3),
	datab => clk_10h(0),
	datac => clk_10h(2),
	datad => clk_10h(1),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10h(3));

\clk_10h[1]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10h(1) = DFFEAS(clk_10h(0) & (!clk_10h(1)) # !clk_10h(0) & clk_10h(1) & (clk_10h(3) # clk_10h(2)), GLOBAL(clk_counter_10h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "32CC",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10h,
	dataa => clk_10h(3),
	datab => clk_10h(0),
	datac => clk_10h(2),
	datad => clk_10h(1),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10h(1));

\clk_10h[2]~I\ : cyclone_lcell
-- Equation(s):
-- clk_10h(2) = DFFEAS(clk_10h(2) $ (clk_10h(1) & clk_10h(0)), GLOBAL(clk_counter_10h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "7878",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10h,
	dataa => clk_10h(1),
	datab => clk_10h(0),
	datac => clk_10h(2),
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_10h(2));

\clk_1h[1]~208_I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[1]~208\ = clk_1h(3) & !clk_1h(1) & !clk_10h(1) # !clk_1h(3) & clk_1h(1) & clk_10h(1) & !clk_10h(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0242",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1h(3),
	datab => clk_1h(1),
	datac => clk_10h(1),
	datad => clk_10h(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \clk_1h[1]~208\);

\clk_1h[1]~206_I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[1]~206\ = !clk_10h(3) & \clk_1h[1]~208\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0F00",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datac => clk_10h(3),
	datad => \clk_1h[1]~208\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \clk_1h[1]~206\);

\clk_1h[1]~216_I\ : cyclone_lcell
-- Equation(s):
-- \clk_1h[1]~216\ = !clk_1h(2) & clk_1h(0) & !clk_10h(2) & \clk_1h[1]~206\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0400",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1h(2),
	datab => clk_1h(0),
	datac => clk_10h(2),
	datad => \clk_1h[1]~206\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \clk_1h[1]~216\);

\clk_1h[1]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1h(1) = DFFEAS(!\clk_1h[1]~216\ & (clk_1h(0) $ clk_1h(1)), GLOBAL(clk_counter_1h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "003C",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1h,
	datab => clk_1h(0),
	datac => clk_1h(1),
	datad => \clk_1h[1]~216\,
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1h(1));

\clk_1h[2]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1h(2) = DFFEAS(!\clk_1h[1]~216\ & (clk_1h(2) $ (clk_1h(0) & clk_1h(1))), GLOBAL(clk_counter_1h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "006A",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1h,
	dataa => clk_1h(2),
	datab => clk_1h(0),
	datac => clk_1h(1),
	datad => \clk_1h[1]~216\,
	aclr => \ALT_INV_reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_1h(2));

\Add4~103_I\ : cyclone_lcell
-- Equation(s):
-- \Add4~103\ = clk_1h(0) & (clk_1h(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "A0A0",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1h(0),
	datac => clk_1h(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Add4~103\);

\clk_1h[3]~I\ : cyclone_lcell
-- Equation(s):
-- clk_1h(3) = DFFEAS(!\clk_1h[1]~216\ & (clk_1h(3) $ (clk_1h(2) & \Add4~103\)), GLOBAL(clk_counter_1h), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0078",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
1234

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