clock.vho

基于SMART-I实验平台的时钟电路设计与实现

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

-- DATE "11/04/2006 14:20:49"

-- 
-- Device: Altera EP1C3T144C6 Package TQFP144
-- 

-- 
-- This VHDL file should be used for Active-HDL (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	clock IS
    PORT (
	clk : IN std_logic;
	reset : IN std_logic;
	LEDOUT : OUT std_logic_vector(7 DOWNTO 0);
	sel : OUT std_logic_vector(2 DOWNTO 0)
	);
END clock;

ARCHITECTURE structure OF clock IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_LEDOUT : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_sel : std_logic_vector(2 DOWNTO 0);
SIGNAL clk_counter_1h : std_logic;
SIGNAL clk_counter_10s : std_logic;
SIGNAL clk_counter_10h : std_logic;
SIGNAL clk_counter_10m : std_logic;
SIGNAL clk_counter_1m : std_logic;
SIGNAL \process4~39\ : std_logic;
SIGNAL \Equal6~38\ : std_logic;
SIGNAL \Equal0~38\ : std_logic;
SIGNAL \Equal4~38\ : std_logic;
SIGNAL \Equal2~38\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \Mux4~24\ : std_logic;
SIGNAL \reset~combout\ : std_logic;
SIGNAL \Mux0~122\ : std_logic;
SIGNAL \clk_1h[1]~208\ : std_logic;
SIGNAL \clk_1h[1]~206\ : std_logic;
SIGNAL \clk_1h[1]~216\ : std_logic;
SIGNAL \Add4~103\ : std_logic;
SIGNAL \Mux0~123\ : std_logic;
SIGNAL \Mux0~124\ : std_logic;
SIGNAL \Mux0~125\ : std_logic;
SIGNAL \Mux3~150\ : std_logic;
SIGNAL \Mux3~148\ : std_logic;
SIGNAL \Mux3~149\ : std_logic;
SIGNAL \Mux3~151\ : std_logic;
SIGNAL \Mux1~124\ : std_logic;
SIGNAL \Mux1~125\ : std_logic;
SIGNAL \Mux1~126\ : std_logic;
SIGNAL \Mux1~127\ : std_logic;
SIGNAL \Mux2~140\ : std_logic;
SIGNAL \Mux2~141\ : std_logic;
SIGNAL \Mux2~142\ : std_logic;
SIGNAL \Mux2~143\ : std_logic;
SIGNAL \Mux11~30\ : std_logic;
SIGNAL \Mux10~29\ : std_logic;
SIGNAL \Mux9~77\ : std_logic;
SIGNAL \Mux8~31\ : std_logic;
SIGNAL \Mux7~49\ : std_logic;
SIGNAL \Mux6~128\ : std_logic;
SIGNAL \Mux5~33\ : std_logic;
SIGNAL clk_10s : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_1h : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_1m : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_1s : std_logic_vector(3 DOWNTO 0);
SIGNAL sel_temp : std_logic_vector(2 DOWNTO 0);
SIGNAL clk_10h : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_10m : std_logic_vector(3 DOWNTO 0);
SIGNAL \ALT_INV_Mux10~29\ : std_logic;
SIGNAL \ALT_INV_Mux9~77\ : std_logic;
SIGNAL \ALT_INV_Mux8~31\ : std_logic;
SIGNAL \ALT_INV_Mux7~49\ : std_logic;
SIGNAL \ALT_INV_Mux5~33\ : std_logic;
SIGNAL \ALT_INV_reset~combout\ : std_logic;

BEGIN

ww_clk <= clk;
ww_reset <= reset;
LEDOUT <= ww_LEDOUT;
sel <= ww_sel;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_Mux10~29\ <= NOT \Mux10~29\;
\ALT_INV_Mux9~77\ <= NOT \Mux9~77\;
\ALT_INV_Mux8~31\ <= NOT \Mux8~31\;
\ALT_INV_Mux7~49\ <= NOT \Mux7~49\;
\ALT_INV_Mux5~33\ <= NOT \Mux5~33\;
\ALT_INV_reset~combout\ <= NOT \reset~combout\;

\clk~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\clk_counter_1h~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_1h = DFFEAS(\Equal6~38\ & (clk_10m(0) & (clk_10m(2)) # !clk_10m(0) & clk_counter_1h) # !\Equal6~38\ & clk_counter_1h, GLOBAL(clk_counter_10m), VCC, , \reset~combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "E4CC",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10m,
	dataa => \Equal6~38\,
	datab => clk_counter_1h,
	datac => clk_10m(2),
	datad => clk_10m(0),
	aclr => GND,
	ena => \reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_counter_1h);

\clk_counter_10s~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_10s = DFFEAS(\Equal0~38\ & (clk_1s(0) & clk_1s(3) # !clk_1s(0) & (clk_counter_10s)) # !\Equal0~38\ & (clk_counter_10s), GLOBAL(\clk~combout\), VCC, , \reset~combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "B8F0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => clk_1s(3),
	datab => \Equal0~38\,
	datac => clk_counter_10s,
	datad => clk_1s(0),
	aclr => GND,
	ena => \reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_counter_10s);

\clk_counter_10h~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_10h = DFFEAS(\clk_1h[1]~216\ # clk_counter_10h & (clk_1h(1) # !\process4~39\), GLOBAL(clk_counter_1h), VCC, , \reset~combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "FF8A",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1h,
	dataa => clk_counter_10h,
	datab => clk_1h(1),
	datac => \process4~39\,
	datad => \clk_1h[1]~216\,
	aclr => GND,
	ena => \reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_counter_10h);

\clk_counter_10m~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_10m = DFFEAS(\Equal4~38\ & (clk_1m(0) & clk_1m(3) # !clk_1m(0) & (clk_counter_10m)) # !\Equal4~38\ & (clk_counter_10m), GLOBAL(clk_counter_1m), VCC, , \reset~combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "B8F0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_1m,
	dataa => clk_1m(3),
	datab => \Equal4~38\,
	datac => clk_counter_10m,
	datad => clk_1m(0),
	aclr => GND,
	ena => \reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_counter_10m);

\clk_counter_1m~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_1m = DFFEAS(clk_10s(0) & (\Equal2~38\ & (clk_10s(2)) # !\Equal2~38\ & clk_counter_1m) # !clk_10s(0) & (clk_counter_1m), GLOBAL(clk_counter_10s), VCC, , \reset~combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "F870",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => clk_counter_10s,
	dataa => clk_10s(0),
	datab => \Equal2~38\,
	datac => clk_counter_1m,
	datad => clk_10s(2),
	aclr => GND,
	ena => \reset~combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clk_counter_1m);

\process4~39_I\ : cyclone_lcell
-- Equation(s):
-- \process4~39\ = clk_1h(0) & !clk_1h(3) & (!clk_1h(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0022",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => clk_1h(0),
	datab => clk_1h(3),
	datad => clk_1h(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \process4~39\);

\Equal6~38_I\ : cyclone_lcell
-- Equation(s):
-- \Equal6~38\ = !clk_10m(1) & !clk_10m(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "000F",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datac => clk_10m(1),
	datad => clk_10m(3),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal6~38\);

\Equal0~38_I\ : cyclone_lcell
-- Equation(s):
-- \Equal0~38\ = !clk_1s(2) & !clk_1s(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "000F",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datac => clk_1s(2),
	datad => clk_1s(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal0~38\);

\Equal4~38_I\ : cyclone_lcell
-- Equation(s):
-- \Equal4~38\ = !clk_1m(1) & !clk_1m(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "000F",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datac => clk_1m(1),
	datad => clk_1m(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal4~38\);

\Equal2~38_I\ : cyclone_lcell
-- Equation(s):
-- \Equal2~38\ = !clk_10s(1) & !clk_10s(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0303",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => clk_10s(1),
	datac => clk_10s(3),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal2~38\);

\sel_temp[0]~I\ : cyclone_lcell
-- Equation(s):
-- sel_temp(0) = DFFEAS(!sel_temp(0), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "00FF",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datad => sel_temp(0),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => sel_temp(0));

\sel_temp[1]~I\ : cyclone_lcell
-- Equation(s):
-- sel_temp(1) = DFFEAS(sel_temp(1) $ sel_temp(0), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0FF0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datac => sel_temp(1),
	datad => sel_temp(0),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => sel_temp(1));

\sel_temp[2]~I\ : cyclone_lcell
-- Equation(s):
-- sel_temp(2) = DFFEAS(sel_temp(2) $ (sel_temp(1) & sel_temp(0)), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3CF0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => sel_temp(1),
	datac => sel_temp(2),
	datad => sel_temp(0),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => sel_temp(2));

\Mux4~24_I\ : cyclone_lcell
-- Equation(s):
-- \Mux4~24\ = !sel_temp(0) & (sel_temp(1) $ sel_temp(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "003C",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => sel_temp(1),
	datac => sel_temp(2),
	datad => sel_temp(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Mux4~24\);

\reset~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",