decode.v

用verilog设计密勒解码器 一、题目： 设计一个密勒解码器电路 二、输入信号： 1． DIN：输入数据 2． CLK：频率为2MHz的方波

module decode(
              //input
              Signal_A,     // detect A
              Signal_B,     // detect B
			     Signal_C,     // detect C
			     BIT_EN_temp,  // bit_enable when detect signal
			     RESET,        // system reset
			     //output
			     DOUT,         // miller decode serial 
			     DATA_EN,      // data_enable
			     BIT_EN        // bit enable when detect effective signal
			     );
input  Signal_A,Signal_B,Signal_C,BIT_EN_temp,RESET;
output DOUT,DATA_EN,BIT_EN;

reg    DOUT,DATA_EN;//,BIT_EN

// signal state
parameter A=2'b00,B=2'b01,C=2'b10;
reg[1:0] last_flag;
reg[1:0] current_flag;
wire[3:0] full_flag;
//wire Signal_det; // indicate we have a "A/B/C detect"

// fsm 3 state
parameter idle = 2'b00, start = 2'b01, data = 2'b10;  
reg[1:0] current_state;
wire[1:0] next_state;

//assign Signal_det = Signal_A|Signal_B|Signal_C;
assign BIT_EN = BIT_EN_temp&DATA_EN;
/*
always @(BIT_EN_temp)
begin
    if(DATA_EN)   //.... up-> 0 and down->1
    BIT_EN<=BIT_EN_temp;
    else
    BIT_EN<=0;
end*/
// aquaire signal state
always @(posedge BIT_EN_temp) //Signal_det) 
begin
  last_flag <= current_flag;
  if (Signal_A)
    begin
      current_flag <= A; 
    end
  else if (Signal_B)
    begin
      current_flag <= B; 
    end
  else 
    begin
      current_flag <= C;  
    end
end
			
assign full_flag = {last_flag,current_flag};

// fsm design
// next state of fsm
assign next_state=fsm_function(full_flag);
function[1:0] fsm_function;
    input[3:0] full_flag;
    case(current_state)
        idle:
            begin
                if(full_flag[1:0]==C) 
                fsm_function=start;
                else
                fsm_function=idle;
            end
        start:
            begin
                if(full_flag=={C,A}||full_flag=={C,C})
                fsm_function=data;
                else
                fsm_function=idle;
            end
        data:
            begin
                if(full_flag=={B,B}||full_flag=={C,B})
                fsm_function=idle;
                else
                fsm_function=data;
            end
        default:fsm_function=idle;
    endcase
endfunction

// current state of fsm
always @(negedge BIT_EN_temp) //Signal_det)
begin
    if(!RESET)
    current_state<=idle;
    else
    current_state<=next_state;
end

// output of fsm
always @(negedge BIT_EN_temp or negedge RESET)//full_flag
begin
    if(!RESET)
       begin
            DATA_EN<=0;
            DOUT<=0;
           // BIT_EN<=0;
            current_flag=B;
       end
    else begin
         case(current_state)
            idle:
                begin
                    DATA_EN<=0;
                    DOUT<=0;
                end
            start:
                /*
                begin
                    case(full_flag)
                        {C,A}:begin DOUT<=1;DATA_EN<=1;end
                        {C,C}:begin DOUT<=0;DATA_EN<=1;end
                        default:begin DOUT<=0;DATA_EN<=0;end
                    endcase
                end*/
                begin
                    DATA_EN<=0;
                    DOUT<=0;
                end
            data:
                begin
                    DATA_EN<=1;
    		              case (full_flag)
 		             // output the front data to avoid getting the stop_signal C errorly
		                   {A,A}: DOUT<=1;
		                   {A,B}: DOUT<=1;
		                   {B,A}: DOUT<=0;
					          {B,C}: DOUT<=0;
					          {C,A}: DOUT<=0;
					          {C,C}: DOUT<=0;
					          default:    begin DATA_EN<=0;DOUT<=0;end
				        endcase	
				    end
				default:
				    begin
				        DATA_EN<=0;
                    DOUT<=0;
                end
		    endcase
		    end  // end case begin
end  // end block of output
                    

endmodule