signal_detect.v

用verilog设计密勒解码器 一、题目： 设计一个密勒解码器电路 二、输入信号： 1． DIN：输入数据 2． CLK：频率为2MHz的方波

`timescale 10ns/1ns
module Signal_detect (
                     //inputs
                     DIN,        // serial data
                     CLK,        // system clock
                     RESET,      // system reset
                     //outputs  
                     Signal_A,   // detect A
                     Signal_B,   // detect B
                     Signal_C,   // detect C
                     BIT_EN_temp // detect A or B or C
                     );
input  DIN,CLK,RESET;
output Signal_A,Signal_B,Signal_C,BIT_EN_temp;

reg Signal_A,Signal_B,Signal_C;
//reg A_BIT_EN,B_BIT_EN,C_BIT_EN; // "BIT_EN" signal

assign BIT_EN_temp = Signal_A|Signal_B|Signal_C;//A_BIT_EN|B_BIT_EN|C_BIT_EN;

parameter A=2'b00,  // state A
          B=2'b01,  // state B
          C=2'b10;  // state C
reg[1:0] state;

reg[4:0] count_temp;  // count the num of H level
reg[4:0] count;       // save the value of "count_temp"

// ouput detected Signal & BIT_EN flag
always @(posedge CLK)
begin
  Signal_A<= 1'b0; Signal_B<= 1'b0; Signal_C<= 1'b0;
 // A_BIT_EN <= 1'b0; B_BIT_EN <= 1'b0; C_BIT_EN <= 1'b0;
  if (count_temp ==5'd1 && state ==A)
    begin
    Signal_A <=1'b1;
 //   A_BIT_EN <=1'b1;
    end
  else if ( (count_temp ==5'd14 || count_temp == 5'd30) && state ==B) // 13,30
    begin   
    Signal_B <=1'b1;
  //  B_BIT_EN <=1'b1;
    end  
  else if (count_temp ==5'd1 && state ==C)
    begin
    Signal_C <= 1'b1;
 //   C_BIT_EN <= 1'b1;
    end
  else
    begin
    Signal_A<= 1'b0; Signal_B<= 1'b0; Signal_C<= 1'b0;
 //   A_BIT_EN <= 1'b0; B_BIT_EN <= 1'b0; C_BIT_EN <= 1'b0;   
    end
end
    
  //ouput BIT_EN flag 
 // A_BIT_EN <= 1'b0; B_BIT_EN <= 1'b0; C_BIT_EN <= 1'b0;
  
//  if (count ==5'd4 && state ==A)
//    a_bit_en <=1'b1;
//  else if ( (count ==8'd16 || count == 8'd29) && state ==B)   
//    b_bit_en <=1'b1;
//  else if (count ==8'd4 && state ==C)
////    c_bit_en <= 1'b1;
//  else
//    begin
//      a_bit_en <= 1'b0; b_bit_en <= 1'b0; c_bit_en <= 1'b0;   
//    end
  //
    
//end

/////////////   count  ////////////////////
always @(negedge DIN or posedge CLK)
begin
  if (!DIN)
    begin
      count  <= 5'b0; 
      count  <= count_temp;
      count_temp <= 5'b0;  
    end  
  else  // posedge of clk
    begin
      if (count_temp >= 5'd31)
        count_temp<=31;
      else 
        count_temp <= count_temp +1;    
    end  
    
  // next B signal
  if (state == A && count_temp == 5'd12) 
      count <= count_temp;   
  if (state == C && count_temp == 5'd20)
      count <= count_temp;   
  //
end


//////////// state Transform  ///////////
//begin C: count       next
//            11         C
//            19         A
//            27,35,>35  BC/BA/BB //end
//begin A: count       next
//            11         A
//            19,27,>27  BC/BA/BB 
//begin B: count       next
//            19         C
//            27         A
//            >27        B   //end
always @(negedge RESET or count or state ) 
begin
  if (!RESET)
    begin
      state = B; count = 5'd0; count_temp =5'd31;  
    end  
  else
    begin
      case (state)
          B:begin
              if (count == 5'd19 || count == 5'd31)
                state = C;
              else if (count == 5'd27)
                state = A;     //
              else state = B;  
            end
          
          A:begin
              if (count == 5'd11)
                state = A;
              else if (count > 5'd11) // ==========================
                state = B;
              else state =A;
            end
          
          C:begin
              if (count == 5'd11)
                state = C;
              else if (count == 5'd19)
                state = A;
              else if (count > 5'd19)
                state =B;
              else state =C;
            end
          
          default:state = B;
      endcase    
    end // end of else
end // end of always block

endmodule