vga_osd_ram.v

在quartusII下用verilog语言自己写的IP核

module	VGA_OSD_RAM	(	//	Read Out Side
                                         oRGB_INDEX,
						iVGA_ADDR,
						iVGA_CLK,
						//	Write In Side
						iWR_DATA,
						iWR_ADDR,
						iWR_EN,
						iWR_CLK,
						//	Control Signals
						iRST_N	);
//	Read Out Side
output	[7:0] 		oRGB_INDEX;
input	[15:0]		iVGA_ADDR;
input				iVGA_CLK;
//	Write In Side
input	[15:0]		iWR_ADDR;
input	[7:0]			iWR_DATA;
input				iWR_EN;
input				iWR_CLK;
//	Control Signals
input				iRST_N;
wire	[7:0]		ROM_DATA;
reg  [7:0] oRGB_INDEX;
always@(posedge iVGA_CLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
       oRGB_INDEX <=0;
	end
	else
	begin
       oRGB_INDEX <=ROM_DATA	;
	end
end

Img_RAM 	u0	(	//	Write In Side
					.data(iWR_DATA),
					.wren(iWR_EN),
					.wraddress(iWR_ADDR),
					.wrclock(iWR_CLK),
					//	Read Out Side
					.rdaddress(iVGA_ADDR),
					.rdclock(iVGA_CLK),
					.q(ROM_DATA));

endmodule