vga_nios_ctrl.v

在quartusII下用verilog语言自己写的IP核

module	VGA_NIOS_CTRL (	//	Host Side
						iDATA,
						oDATA,
						iADDR,
						iWR,
						iRD,
						iCS,
						iRST_N,
						iCLK,		//	Host Clock
						//	Export Side
						VGA_R,
						VGA_G,
						VGA_B,
						VGA_HS,
						VGA_VS,
						VGA_SYNC,
						VGA_BLANK,
						VGA_CLK,
						iCLK_27,
                                          oclk_27	
                                            );

//parameter	RAM_SIZE	=	19'h4B000;

//	Host Side
output	[31:0]	oDATA;
input	[31:0]	iDATA;	
input [15:0]	iADDR;
input			iWR,iRD,iCS;
input			iCLK,iRST_N;
reg		[31:0]	oDATA;
//	Export Side
output	[9:0]	VGA_R;
output	[9:0]	VGA_G;
output	[9:0]	VGA_B;
output			VGA_HS;
output              oclk_27;
output			VGA_VS;
output			VGA_SYNC;
output			VGA_BLANK;
output			VGA_CLK;
input			iCLK_27;
wire	[15:0]	mVGA_ADDR;
//reg     [29:0] palette[256:0];
reg     [15:0]  palindex;
parameter BASE=16'd32400;
wire    [7:0]  RGB_INDEX;
wire    [8:0]  RGB_INDEX1;
wire    [29:0]  rgb;
//integer i;
//assign   rgb=palette[RGB_INDEX1];
//assign   VGA_R=rgb[9:0];                   //???????????????????
//assign   VGA_G=rgb[19:10];
//assign   VGA_B=rgb[29:20];





/*always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
	              //缺省的调色板的值
      palindex  <=  0;
      //for(i=0;i<257;i=i+1)
     // palette[i] <= i*4177983;
	end
	else
	begin
		if(iCS&&(iADDR>=BASE)&&(iADDR<=BASE+256))
		begin
                     palindex=iADDR-BASE;
			if(iWR)
			palette[palindex[8:0]]=iDATA[29:0];
			else if(iRD)
			oDATA[31:0]={2'b00,palette[palindex[8:0]]};
		end
	end
end

*/


 palette  u2 (                                   //调色板
	.data(iDATA),
	.rdaddress(RGB_INDEX1),
	.rdclock(iCLK_27),
	.wraddress(iADDR-BASE),
	.wrclock(iCLK),
	.wren(iCS&&(iADDR>=BASE)&&(iADDR<=BASE+256)),
	.q({VGA_B,VGA_G,VGA_R}));











VGA_Controller		u0	(	//	Host Side							
								.oAddress(mVGA_ADDR),
                                .iRGB_INDEX(RGB_INDEX),
								//	VGA Side
                                .oRGB_INDEX(RGB_INDEX1),
								.oVGA_H_SYNC(VGA_HS),
								.oVGA_V_SYNC(VGA_VS),
								.oVGA_SYNC(VGA_SYNC),
								.oVGA_BLANK(VGA_BLANK),
								.oVGA_CLOCK(VGA_CLK),
								//	Control Signal
								.iCLK_27(iCLK_27),
								.iRST_N(iRST_N),
                                .oclk_27(oclk_27)	
                                                        );

VGA_OSD_RAM			u1	(	//	Read Out Side
                            .oRGB_INDEX(RGB_INDEX),
							.iVGA_ADDR(mVGA_ADDR),
							.iVGA_CLK(VGA_CLK),
							//	Write In Side
							.iWR_DATA(iDATA[7:0]),
							.iWR_ADDR(iADDR),
							.iWR_EN(iWR && iCS&&(iADDR<BASE)),
							.iWR_CLK(iCLK),
							//	Control Signals
							.iRST_N(iRST_N)	);
								
endmodule