📄 elec_lock.rpt
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-- Node name is ':95' = 'REG7'
-- Equation name is 'REG7', location is LC051, type is buried.
REG7 = TFFE( _EQ039, Q0, VCC, VCC, VCC);
_EQ039 = ACC7 & !ENLOCK & F2 & !REG7
# !ACC7 & !ENLOCK & F2 & REG7;
-- Node name is ':94' = 'REG8'
-- Equation name is 'REG8', location is LC050, type is buried.
REG8 = TFFE( _EQ040, Q0, VCC, VCC, VCC);
_EQ040 = ACC8 & !ENLOCK & F2 & !REG8
# !ACC8 & !ENLOCK & F2 & REG8;
-- Node name is ':93' = 'REG9'
-- Equation name is 'REG9', location is LC049, type is buried.
REG9 = TFFE( _EQ041, Q0, VCC, VCC, VCC);
_EQ041 = ACC9 & !ENLOCK & F2 & !REG9
# !ACC9 & !ENLOCK & F2 & REG9;
-- Node name is ':92' = 'REG10'
-- Equation name is 'REG10', location is LC052, type is buried.
REG10 = TFFE( _EQ042, Q0, VCC, VCC, VCC);
_EQ042 = ACC10 & !ENLOCK & F2 & !REG10
# !ACC10 & !ENLOCK & F2 & REG10;
-- Node name is ':91' = 'REG11'
-- Equation name is 'REG11', location is LC053, type is buried.
REG11 = TFFE( _EQ043, Q0, VCC, VCC, VCC);
_EQ043 = ACC11 & !ENLOCK & F2 & !REG11
# !ACC11 & !ENLOCK & F2 & REG11;
-- Node name is ':90' = 'REG12'
-- Equation name is 'REG12', location is LC054, type is buried.
REG12 = TFFE( _EQ044, Q0, VCC, VCC, VCC);
_EQ044 = ACC12 & !ENLOCK & F2 & !REG12
# !ACC12 & !ENLOCK & F2 & REG12;
-- Node name is ':89' = 'REG13'
-- Equation name is 'REG13', location is LC056, type is buried.
REG13 = TFFE( _EQ045, Q0, VCC, VCC, VCC);
_EQ045 = ACC13 & !ENLOCK & F2 & !REG13
# !ACC13 & !ENLOCK & F2 & REG13;
-- Node name is ':88' = 'REG14'
-- Equation name is 'REG14', location is LC062, type is buried.
REG14 = TFFE( _EQ046, Q0, VCC, VCC, VCC);
_EQ046 = ACC14 & !ENLOCK & F2 & !REG14
# !ACC14 & !ENLOCK & F2 & REG14;
-- Node name is ':87' = 'REG15'
-- Equation name is 'REG15', location is LC061, type is buried.
REG15 = TFFE( _EQ047, Q0, VCC, VCC, VCC);
_EQ047 = ACC15 & !ENLOCK & F2 & !REG15
# !ACC15 & !ENLOCK & F2 & REG15;
-- Node name is '|debouncing:U1|dff1'
-- Equation name is '_LC031', type is buried
_LC031 = DFFE( GND $ VCC, Q0, !KEY_IN0, VCC, VCC);
-- Node name is '|debouncing:U1|dff2'
-- Equation name is '_LC030', type is buried
_LC030 = DFFE( GND $ VCC, Q0, _LC031, VCC, VCC);
-- Node name is '|debouncing:U1|:8' = '|debouncing:U1|d0'
-- Equation name is '_LC019', type is buried
_LC019 = DFFE(!_LC030 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U1|:9' = '|debouncing:U1|d1'
-- Equation name is '_LC008', type is buried
_LC008 = DFFE( _LC019 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U2|dff1'
-- Equation name is '_LC020', type is buried
_LC020 = DFFE( GND $ VCC, Q0, !KEY_IN1, VCC, VCC);
-- Node name is '|debouncing:U2|dff2'
-- Equation name is '_LC021', type is buried
_LC021 = DFFE( GND $ VCC, Q0, _LC020, VCC, VCC);
-- Node name is '|debouncing:U2|:8' = '|debouncing:U2|d0'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE(!_LC021 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U2|:9' = '|debouncing:U2|d1'
-- Equation name is '_LC016', type is buried
_LC016 = DFFE( _LC022 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U3|dff1'
-- Equation name is '_LC024', type is buried
_LC024 = DFFE( GND $ VCC, Q0, !KEY_IN2, VCC, VCC);
-- Node name is '|debouncing:U3|dff2'
-- Equation name is '_LC028', type is buried
_LC028 = DFFE( GND $ VCC, Q0, _LC024, VCC, VCC);
-- Node name is '|debouncing:U3|:8' = '|debouncing:U3|d0'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE(!_LC028 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U3|:9' = '|debouncing:U3|d1'
-- Equation name is '_LC015', type is buried
_LC015 = DFFE( _LC029 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '~1229~1'
-- Equation name is '~1229~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ048 $ _EQ049);
_EQ048 = !ACC0 & !_LC040 & !_LC042 & !_LC057 & REG0 & _X008 & _X009 &
_X010 & _X011 & _X012 & _X013 & _X014 & _X015 & _X016 &
_X017 & _X018 & _X019 & _X020
# ACC0 & !_LC040 & !_LC042 & !_LC057 & !REG0 & _X008 & _X009 &
_X010 & _X011 & _X012 & _X013 & _X014 & _X015 & _X016 &
_X017 & _X018 & _X019 & _X020
# !ACC1 & !_LC040 & !_LC042 & !_LC057 & REG1 & _X008 & _X009 &
_X010 & _X011 & _X012 & _X013 & _X014 & _X015 & _X016 &
_X017 & _X018 & _X019 & _X020
# ACC1 & !_LC040 & !_LC042 & !_LC057 & !REG1 & _X008 & _X009 &
_X010 & _X011 & _X012 & _X013 & _X014 & _X015 & _X016 &
_X017 & _X018 & _X019 & _X020;
_X008 = EXP(!ACC12 & REG12);
_X009 = EXP( ACC9 & !REG9);
_X010 = EXP(!ACC10 & REG10);
_X011 = EXP( ACC15 & !REG15);
_X012 = EXP(!ACC15 & REG15);
_X013 = EXP( ACC14 & !REG14);
_X014 = EXP(!ACC14 & REG14);
_X015 = EXP( ACC13 & !REG13);
_X016 = EXP(!ACC13 & REG13);
_X017 = EXP( ACC12 & !REG12);
_X018 = EXP( ACC10 & !REG10);
_X019 = EXP( ACC11 & !REG11);
_X020 = EXP(!ACC11 & REG11);
_EQ049 = !_LC040 & !_LC042 & !_LC057 & _X008 & _X009 & _X010 & _X011 &
_X012 & _X013 & _X014 & _X015 & _X016 & _X017 & _X018 &
_X019 & _X020;
_X008 = EXP(!ACC12 & REG12);
_X009 = EXP( ACC9 & !REG9);
_X010 = EXP(!ACC10 & REG10);
_X011 = EXP( ACC15 & !REG15);
_X012 = EXP(!ACC15 & REG15);
_X013 = EXP( ACC14 & !REG14);
_X014 = EXP(!ACC14 & REG14);
_X015 = EXP( ACC13 & !REG13);
_X016 = EXP(!ACC13 & REG13);
_X017 = EXP( ACC12 & !REG12);
_X018 = EXP( ACC10 & !REG10);
_X019 = EXP( ACC11 & !REG11);
_X020 = EXP(!ACC11 & REG11);
-- Node name is '~1229~2'
-- Equation name is '~1229~2', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ050 $ GND);
_EQ050 = !ACC2 & REG2
# ACC2 & !REG2
# !ACC3 & REG3
# ACC3 & !REG3
# !ACC4 & REG4;
-- Node name is '~1229~3'
-- Equation name is '~1229~3', location is LC040, type is buried.
-- synthesized logic cell
_LC040 = LCELL( _EQ051 $ GND);
_EQ051 = ACC4 & !REG4
# !ACC5 & REG5
# ACC5 & !REG5
# !ACC6 & REG6
# ACC6 & !REG6;
-- Node name is '~1229~4'
-- Equation name is '~1229~4', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ052 $ GND);
_EQ052 = !ACC7 & REG7
# ACC7 & !REG7
# !ACC8 & REG8
# ACC8 & !REG8
# !ACC9 & REG9;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs B, C, D
Project Information f:\test1_last\elec_lock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,926K
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