📄 elec_lock.rpt
字号:
Project Information f:\test1_last\elec_lock.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 04/05/2007 11:44:22
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
ELEC_LOCK
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
elec_lock
EPM7064SLC44-10 4 5 0 64 22 100%
User Pins: 4 5 0
Project Information f:\test1_last\elec_lock.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'RST'
Project Information f:\test1_last\elec_lock.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK_4M' chosen for auto global Clock
Project Information f:\test1_last\elec_lock.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
elec_lock@9 CLK_SCAN0
elec_lock@8 CLK_SCAN1
elec_lock@6 CLK_SCAN2
elec_lock@5 CLK_SCAN3
elec_lock@43 CLK_4M
elec_lock@16 ENLOCK
elec_lock@11 KEY_IN0
elec_lock@12 KEY_IN1
elec_lock@14 KEY_IN2
Project Information f:\test1_last\elec_lock.rpt
** FILE HIERARCHY **
|lpm_add_sub:173|
|lpm_add_sub:173|addcore:adder|
|lpm_add_sub:173|addcore:adder|addcore:adder2|
|lpm_add_sub:173|addcore:adder|addcore:adder1|
|lpm_add_sub:173|addcore:adder|addcore:adder0|
|lpm_add_sub:173|altshift:result_ext_latency_ffs|
|lpm_add_sub:173|altshift:carry_ext_latency_ffs|
|lpm_add_sub:173|altshift:oflow_ext_latency_ffs|
|debouncing:U1|
|debouncing:U2|
|debouncing:U3|
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
***** Logic for device 'elec_lock' compiled without errors.
Device: EPM7064SLC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** ERROR SUMMARY **
Info: Chip 'elec_lock' in device 'EPM7064SLC44-10' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
C C
L L R R R
K K E E E
_ _ S C S S
S S E L E E
C C R K R R
A A V V G G G _ G V V
N N E C N N N 4 N E E
2 3 D C D D D M D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | RESERVED
CLK_SCAN1 | 8 38 | #TDO
CLK_SCAN0 | 9 37 | RESERVED
GND | 10 36 | RESERVED
KEY_IN0 | 11 35 | VCC
KEY_IN1 | 12 EPM7064SLC44-10 34 | RESERVED
#TMS | 13 33 | RESERVED
KEY_IN2 | 14 32 | #TCK
VCC | 15 31 | RESERVED
ENLOCK | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 7/ 8( 87%) 10/16( 62%) 11/36( 30%)
B: LC17 - LC32 16/16(100%) 3/ 8( 37%) 2/16( 12%) 22/36( 61%)
C: LC33 - LC48 16/16(100%) 1/ 8( 12%) 3/16( 18%) 17/36( 47%)
D: LC49 - LC64 16/16(100%) 1/ 8( 12%) 16/16(100%) 32/36( 88%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 12/32 ( 37%)
Total logic cells used: 64/64 (100%)
Total shareable expanders used: 22/64 ( 34%)
Total Turbo logic cells used: 64/64 (100%)
Total shareable expanders not available (n/a): 9/64 ( 14%)
Average fan-in: 4.78
Total fan-in: 306
Total input pins required: 4
Total fast input logic cells required: 0
Total output pins required: 5
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 64
Total flipflops required: 56
Total product terms required: 194
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 20
Synthesized logic cells: 4/ 64 ( 6%)
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 CLK_4M
11 (3) (A) INPUT 0 0 0 0 0 0 1 KEY_IN0
12 (1) (A) INPUT 0 0 0 0 0 0 1 KEY_IN1
14 (30) (B) INPUT 0 0 0 0 0 0 1 KEY_IN2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
9 4 A OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN0
8 5 A OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN1
6 11 A OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN2
5 14 A OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN3
16 25 B FF t 1 0 0 0 5 1 16 ENLOCK
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 31 B DFFE t 0 0 0 1 1 0 1 |debouncing:U1|dff1
(14) 30 B DFFE t 0 0 0 0 2 0 1 |debouncing:U1|dff2
(20) 19 B DFFE t 0 0 0 0 2 0 7 |debouncing:U1|d0 (|debouncing:U1|:8)
(7) 8 A DFFE t 0 0 0 0 2 0 6 |debouncing:U1|d1 (|debouncing:U1|:9)
(19) 20 B DFFE t 0 0 0 1 1 0 1 |debouncing:U2|dff1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -