dpll.map.summary

来自「用一片CPLD实现数字锁相环,用VHDL或V语言.」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Tue Mar 20 22:11:48 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dpll
Top-level Entity Name : dpll
Family : Stratix
Total logic elements : 95
Total pins : 5
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0