lac_adder16.tan.rpt

十六位超前进位加法器

Timing Analyzer report for LAC_adder16
Sun Nov 27 00:00:42 2005
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Minimum tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                  ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 15.507 ns   ; b[2] ; s[15] ; --         ; --       ; 0            ;
; Worst-case Minimum tpd       ; N/A   ; None          ; 8.064 ns    ; b[0] ; s[0]  ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;       ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C6        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-------+-------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From  ; To    ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-------+-------+
; N/A                                     ; None                                                ; 15.507 ns       ; b[2]  ; s[15] ;
; N/A                                     ; None                                                ; 15.325 ns       ; b[2]  ; s[11] ;
; N/A                                     ; None                                                ; 15.307 ns       ; b[2]  ; s[6]  ;
; N/A                                     ; None                                                ; 15.242 ns       ; a[2]  ; s[15] ;
; N/A                                     ; None                                                ; 15.209 ns       ; b[2]  ; s[7]  ;
; N/A                                     ; None                                                ; 15.147 ns       ; a[1]  ; s[6]  ;
; N/A                                     ; None                                                ; 15.096 ns       ; a[1]  ; s[15] ;
; N/A                                     ; None                                                ; 15.060 ns       ; a[2]  ; s[11] ;
; N/A                                     ; None                                                ; 15.057 ns       ; b[3]  ; s[6]  ;
; N/A                                     ; None                                                ; 15.049 ns       ; a[1]  ; s[7]  ;
; N/A                                     ; None                                                ; 15.043 ns       ; b[3]  ; s[15] ;
; N/A                                     ; None                                                ; 15.042 ns       ; a[2]  ; s[6]  ;
; N/A                                     ; None                                                ; 14.965 ns       ; b[2]  ; s[14] ;
; N/A                                     ; None                                                ; 14.959 ns       ; b[3]  ; s[7]  ;
; N/A                                     ; None                                                ; 14.944 ns       ; a[2]  ; s[7]  ;
; N/A                                     ; None                                                ; 14.861 ns       ; b[3]  ; s[11] ;
; N/A                                     ; None                                                ; 14.842 ns       ; a[3]  ; s[6]  ;
; N/A                                     ; None                                                ; 14.828 ns       ; a[3]  ; s[15] ;
; N/A                                     ; None                                                ; 14.805 ns       ; a[1]  ; s[14] ;
; N/A                                     ; None                                                ; 14.744 ns       ; a[3]  ; s[7]  ;
; N/A                                     ; None                                                ; 14.735 ns       ; b[2]  ; s[13] ;
; N/A                                     ; None                                                ; 14.724 ns       ; b[1]  ; s[6]  ;
; N/A                                     ; None                                                ; 14.715 ns       ; b[3]  ; s[14] ;
; N/A                                     ; None                                                ; 14.700 ns       ; a[2]  ; s[14] ;
; N/A                                     ; None                                                ; 14.673 ns       ; b[1]  ; s[15] ;
; N/A                                     ; None                                                ; 14.646 ns       ; a[3]  ; s[11] ;
; N/A                                     ; None                                                ; 14.626 ns       ; b[1]  ; s[7]  ;
; N/A                                     ; None                                                ; 14.612 ns       ; a[1]  ; s[11] ;