lac_adder16.map.qmsg

十六位超前进位加法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 27 00:00:25 2005 " "Info: Processing started: Sun Nov 27 00:00:25 2005" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LAC_adder16 -c LAC_adder16 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LAC_adder16 -c LAC_adder16" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../LAC_adder4/LAC_adder4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../LAC_adder4/LAC_adder4.v" { { "Info" "ISGN_ENTITY_NAME" "1 LAC_adder4 " "Info: Found entity 1: LAC_adder4" {  } { { "../LAC_adder4/LAC_adder4.v" "" { Text "D:/documents/FPGA/study/LAC_adder4/LAC_adder4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LAC_adder16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LAC_adder16.v" { { "Info" "ISGN_ENTITY_NAME" "1 LAC_adder16 " "Info: Found entity 1: LAC_adder16" {  } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "LAC_adder16 " "Info: Elaborating entity \"LAC_adder16\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LAC_adder4 LAC_adder4:comb_4 " "Info: Elaborating entity \"LAC_adder4\" for hierarchy \"LAC_adder4:comb_4\"" {  } { { "LAC_adder16.v" "comb_4" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 9 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "127 " "Info: Implemented 127 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "33 " "Info: Implemented 33 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "76 " "Info: Implemented 76 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 27 00:00:30 2005 " "Info: Processing ended: Sun Nov 27 00:00:30 2005" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}