lac_adder16.tan.qmsg

十六位超前进位加法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 27 00:00:41 2005 " "Info: Processing started: Sun Nov 27 00:00:41 2005" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off LAC_adder16 -c LAC_adder16 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LAC_adder16 -c LAC_adder16 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[2\] s\[15\] 15.507 ns Longest " "Info: Longest tpd from source pin \"b\[2\]\" to destination pin \"s\[15\]\" is 15.507 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns b\[2\] 1 PIN PIN_128 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_128; Fanout = 3; PIN Node = 'b\[2\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[2] } "NODE_NAME" } "" } } { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.236 ns) + CELL(0.088 ns) 6.459 ns LAC_adder4:comb_4\|p\[2\] 2 COMB LC_X17_Y5_N2 4 " "Info: 2: + IC(5.236 ns) + CELL(0.088 ns) = 6.459 ns; Loc. = LC_X17_Y5_N2; Fanout = 4; COMB Node = 'LAC_adder4:comb_4\|p\[2\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "5.324 ns" { b[2] LAC_adder4:comb_4|p[2] } "NODE_NAME" } "" } } { "../LAC_adder4/LAC_adder4.v" "" { Text "D:/documents/FPGA/study/LAC_adder4/LAC_adder4.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.454 ns) 7.893 ns LAC_adder4:comb_4\|g_out~168 3 COMB LC_X17_Y4_N6 6 " "Info: 3: + IC(0.980 ns) + CELL(0.454 ns) = 7.893 ns; Loc. = LC_X17_Y4_N6; Fanout = 6; COMB Node = 'LAC_adder4:comb_4\|g_out~168'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "1.434 ns" { LAC_adder4:comb_4|p[2] LAC_adder4:comb_4|g_out~168 } "NODE_NAME" } "" } } { "../LAC_adder4/LAC_adder4.v" "" { Text "D:/documents/FPGA/study/LAC_adder4/LAC_adder4.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.340 ns) 9.444 ns c~142 4 COMB LC_X19_Y5_N0 2 " "Info: 4: + IC(1.211 ns) + CELL(0.340 ns) = 9.444 ns; Loc. = LC_X19_Y5_N0; Fanout = 2; COMB Node = 'c~142'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "1.551 ns" { LAC_adder4:comb_4|g_out~168 c~142 } "NODE_NAME" } "" } } { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.088 ns) 9.863 ns c~11 5 COMB LC_X19_Y5_N3 4 " "Info: 5: + IC(0.331 ns) + CELL(0.088 ns) = 9.863 ns; Loc. = LC_X19_Y5_N3; Fanout = 4; COMB Node = 'c~11'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "0.419 ns" { c~142 c~11 } "NODE_NAME" } "" } } { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(0.225 ns) 11.319 ns LAC_adder4:comb_23\|c~109 6 COMB LC_X24_Y7_N8 1 " "Info: 6: + IC(1.231 ns) + CELL(0.225 ns) = 11.319 ns; Loc. = LC_X24_Y7_N8; Fanout = 1; COMB Node = 'LAC_adder4:comb_23\|c~109'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "1.456 ns" { c~11 LAC_adder4:comb_23|c~109 } "NODE_NAME" } "" } } { "../LAC_adder4/LAC_adder4.v" "" { Text "D:/documents/FPGA/study/LAC_adder4/LAC_adder4.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.340 ns) 12.478 ns LAC_adder4:comb_23\|s\[3\] 7 COMB LC_X23_Y7_N2 1 " "Info: 7: + IC(0.819 ns) + CELL(0.340 ns) = 12.478 ns; Loc. = LC_X23_Y7_N2; Fanout = 1; COMB Node = 'LAC_adder4:comb_23\|s\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "1.159 ns" { LAC_adder4:comb_23|c~109 LAC_adder4:comb_23|s[3] } "NODE_NAME" } "" } } { "../LAC_adder4/LAC_adder4.v" "" { Text "D:/documents/FPGA/study/LAC_adder4/LAC_adder4.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.395 ns) + CELL(1.634 ns) 15.507 ns s\[15\] 8 PIN PIN_97 0 " "Info: 8: + IC(1.395 ns) + CELL(1.634 ns) = 15.507 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 's\[15\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "3.029 ns" { LAC_adder4:comb_23|s[3] s[15] } "NODE_NAME" } "" } } { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.304 ns ( 27.76 % ) " "Info: Total cell delay = 4.304 ns ( 27.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.203 ns ( 72.24 % ) " "Info: Total interconnect delay = 11.203 ns ( 72.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "15.507 ns" { b[2] LAC_adder4:comb_4|p[2] LAC_adder4:comb_4|g_out~168 c~142 c~11 LAC_adder4:comb_23|c~109 LAC_adder4:comb_23|s[3] s[15] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "15.507 ns" { b[2] b[2]~out0 LAC_adder4:comb_4|p[2] LAC_adder4:comb_4|g_out~168 c~142 c~11 LAC_adder4:comb_23|c~109 LAC_adder4:comb_23|s[3] s[15] } { 0.000ns 0.000ns 5.236ns 0.980ns 1.211ns 0.331ns 1.231ns 0.819ns 1.395ns } { 0.000ns 1.135ns 0.088ns 0.454ns 0.340ns 0.088ns 0.225ns 0.340ns 1.634ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[0\] s\[0\] 8.064 ns Shortest " "Info: Shortest tpd from source pin \"b\[0\]\" to destination pin \"s\[0\]\" is 8.064 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns b\[0\] 1 PIN PIN_55 7 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_55; Fanout = 7; PIN Node = 'b\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[0] } "NODE_NAME" } "" } } { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.896 ns) + CELL(0.088 ns) 5.119 ns LAC_adder4:comb_4\|s\[0\] 2 COMB LC_X17_Y1_N2 1 " "Info: 2: + IC(3.896 ns) + CELL(0.088 ns) = 5.119 ns; Loc. = LC_X17_Y1_N2; Fanout = 1; COMB Node = 'LAC_adder4:comb_4\|s\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "3.984 ns" { b[0] LAC_adder4:comb_4|s[0] } "NODE_NAME" } "" } } { "../LAC_adder4/LAC_adder4.v" "" { Text "D:/documents/FPGA/study/LAC_adder4/LAC_adder4.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.323 ns) + CELL(1.622 ns) 8.064 ns s\[0\] 3 PIN PIN_54 0 " "Info: 3: + IC(1.323 ns) + CELL(1.622 ns) = 8.064 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 's\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "2.945 ns" { LAC_adder4:comb_4|s[0] s[0] } "NODE_NAME" } "" } } { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.845 ns ( 35.28 % ) " "Info: Total cell delay = 2.845 ns ( 35.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.219 ns ( 64.72 % ) " "Info: Total interconnect delay = 5.219 ns ( 64.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "8.064 ns" { b[0] LAC_adder4:comb_4|s[0] s[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "8.064 ns" { b[0] b[0]~out0 LAC_adder4:comb_4|s[0] s[0] } { 0.000ns 0.000ns 3.896ns 1.323ns } { 0.000ns 1.135ns 0.088ns 1.622ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 27 00:00:42 2005 " "Info: Processing ended: Sun Nov 27 00:00:42 2005" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}