ddr sdram controller.htm

DDR RAM控制器的VHDL源码

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          <TD class=pagetitle>Lattice Reference Designs<BR></TD></TR>
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                  <H2>DDR SDRAM Controller</H2>
                  <P><IMG hspace=5 
                  src="DDR SDRAM Controller.files/ref_design_logo.gif" 
                  align=right vspace=5>The DDR SDRAM uses double data rate 
                  architecture to achieve high-speed data transfers. DDR SDRAM ( 
                  referred to as DDR) transfers data on both the rising and 
                  falling edge of the clock. This reference design provides an 
                  implementation of the DDR memory controller implemented in 
                  Lattice ORCA Series 4 FPGA device. This DDR controller is 
                  typically implemented in a system between the DDR and the bus 
                  master. Figure 1 shows the relationship of the controller 
                  between the bus master and the DDR. The bus master could be 
                  either a microprocessor like Intel's i960 or a user's 
                  proprietary module interface. For illustration purpose, the 
                  Micron's 4M x 8 x 4Banks DDR SDRAM is chosen for this design. 
                  The design was verified using Micron SDRAM simulation model. 
                  </P></TD></TR>
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                <TD colSpan=6><IMG 
                  src="DDR SDRAM Controller.files/ddr_controller.gif"></TD></TR>
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                <TD vAlign=bottom><STRONG><U>Language</U></STRONG></TD>
                <TD vAlign=bottom><STRONG><U>Max. Freq.</U></STRONG></TD>
                <TD vAlign=bottom><STRONG><U>I/O</U></STRONG></TD>
                <TD vAlign=bottom><STRONG><U>PFU</U></STRONG></TD>
                <TD vAlign=bottom><STRONG><U>Register</U></STRONG></TD>
                <TD 
              vAlign=bottom><STRONG><U>Device</U><SUP>*</SUP></STRONG></TD></TR>
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                <TD vAlign=top>Verilog</TD>
                <TD vAlign=top>147MHz (w/PLL)</TD>
                <TD vAlign=top>80/405</TD>
                <TD vAlign=top>50/624</TD>
                <TD vAlign=top>249</TD>
                <TD vAlign=top>OR4E02-2</TD></TR>
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                <TD colSpan=6><A 
                  href="http://www.latticesemi.com/account/_download.cfm?AMID=8492"><IMG 
                  alt=PDF src="DDR SDRAM Controller.files/pdfmid.gif" 
                  align=middle border=0> download design documentation</A><BR><A 
                  href="http://www.latticesemi.com/account/_download.cfm?AMID=8493"><IMG 
                  alt="Source Code" 
                  src="DDR SDRAM Controller.files/diskette.gif" align=middle 
                  border=0> download source code</A><BR></TD></TR>
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                <TD colSpan=6><SUP>*</SUP> May work in other devices as 
                well.</TD></TR>
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                <TD colSpan=6><STRONG>Note:</STRONG> <EM>The performance and 
                  design sizes shown above are estimates only. The actual 
                  results may vary depending upon the chosen parameters, timing 
                  constraints, and device implementation. See the design's 
                  documentation for details. All coding and design work was done 
                  on a PC platform unless noted otherwise.</EM> 
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