📄 mc8051_tmrctr_rtl.vhd
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-- This section generates the timer/counter overflow flag0 if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then if s_count0 = conv_unsigned(65311,16) then -- *** s_tf0 <= '1'; else s_tf0 <= '0'; end if; end if; end if; end if; -- This section generates the low byte register of tmr/ctr0 if wt_i = "00" and wt_en_i = '1' then s_countl0 <= unsigned(reload_i); else if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' then if s_countl0 = conv_unsigned(31,8) then -- *** s_countl0 <= conv_unsigned(0,8); else s_countl0 <= s_countl0 + conv_unsigned(1,1); end if; else if s_ext_edge0 = '1' then if s_countl0 = conv_unsigned(31,8) then -- *** s_countl0 <= conv_unsigned(0,8); else s_countl0 <= s_countl0 + conv_unsigned(1,1); end if; end if; end if; end if; end if; end if; -- This section generates the high byte register of tmr/ctr0 if wt_i = "10" and wt_en_i = '1' then s_counth0 <= unsigned(reload_i); else if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' then if s_count0 = conv_unsigned(65311,16) then -- *** s_counth0 <= conv_unsigned(0,8); else if s_countl0 = conv_unsigned(31,8) then -- *** s_counth0 <= s_counth0 + conv_unsigned(1,1); end if; end if; else if s_ext_edge0 = '1' then if s_count0 = conv_unsigned(65311,16) then -- *** s_counth0 <= conv_unsigned(0,8); else if s_countl0 = conv_unsigned(31,8) then -- *** s_counth0 <= s_counth0 + conv_unsigned(1,1); end if; end if; end if; end if; end if; end if; end if;--------------------------------------------------------------------------------- operating mode 1 (16 bit timer/counter)------------------------------------------------------------------------------- when "01" => -- This section generates the timer/counter overflow flag0 if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then if s_count0 = conv_unsigned(65535,16) then s_tf0 <= '1'; else s_tf0 <= '0'; end if; end if; end if; end if; -- This section generates the low byte register of tmr/ctr0 if wt_i = "00" and wt_en_i = '1' then s_countl0 <= unsigned(reload_i); else if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' then if s_count0 = conv_unsigned(65535,16) then s_countl0 <= conv_unsigned(0,8); else s_countl0 <= s_countl0 + conv_unsigned(1,1); end if; else if s_ext_edge0 = '1' then if s_count0 = conv_unsigned(65535,16) then s_countl0 <= conv_unsigned(0,8); else s_countl0 <= s_countl0 + conv_unsigned(1,1); end if; end if; end if; end if; end if; end if; -- This section generates the high byte register of tmr/ctr0 if wt_i = "10" and wt_en_i = '1' then s_counth0 <= unsigned(reload_i); else if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' then if s_count0 = conv_unsigned(65535,16) then s_counth0 <= conv_unsigned(0,8); else if s_countl0 = conv_unsigned(255,8) then s_counth0 <= s_counth0 + conv_unsigned(1,1); end if; end if; else if s_ext_edge0 = '1' then if s_count0 = conv_unsigned(65535,16) then s_counth0 <= conv_unsigned(0,8); else if s_countl0 = conv_unsigned(255,8) then s_counth0 <= s_counth0 + conv_unsigned(1,1); end if; end if; end if; end if; end if; end if; end if;--------------------------------------------------------------------------------- operating mode 2 (8 bit timer/counter, autoreloaded from high byte register)------------------------------------------------------------------------------- when "10" => -- This section generates the timer/counter overflow flag0 if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then if s_count0(7 downto 0) = conv_unsigned(255,16) then s_tf0 <= '1'; else s_tf0 <= '0'; end if; end if; end if; end if; -- This section generates the low byte register of tmr/ctr0 if wt_i = "00" and wt_en_i = '1' then s_countl0 <= unsigned(reload_i); else if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' then if s_countl0 = conv_unsigned(255,8) then s_countl0 <= s_counth0; else s_countl0 <= s_countl0 + conv_unsigned(1,1); end if; else if s_ext_edge0 = '1' then if s_countl0 = conv_unsigned(255,8) then s_countl0 <= s_counth0; else s_countl0 <= s_countl0 + conv_unsigned(1,1); end if; end if; end if; end if; end if; end if; -- This section generates the high byte register of tmr/ctr0 if wt_i = "10" and wt_en_i = '1' then s_counth0 <= unsigned(reload_i); end if; --------------------------------------------------------------------------------- operating mode 3 (One 8 bit timer/counter and one 8 bit timer)------------------------------------------------------------------------------- when "11" => -- This section generates the timer/counter overflow flag0 if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then if s_count0(7 downto 0) = conv_unsigned(255,16) then s_tf0 <= '1'; else s_tf0 <= '0'; end if; end if; end if; end if; -- This section generates the low byte register of tmr/ctr0 if wt_i = "00" and wt_en_i = '1' then s_countl0 <= unsigned(reload_i); else if s_tmr_ctr0_en = '1' then if s_count_enable = '1' then if s_c_t0 = '0' then if s_countl0 = conv_unsigned(255,8) then s_countl0 <= conv_unsigned(0,8); else s_countl0 <= s_countl0 + conv_unsigned(1,1); end if; else if s_ext_edge0 = '1' then if s_countl0 = conv_unsigned(255,8) then s_countl0 <= conv_unsigned(0,8); else s_countl0 <= s_countl0 + conv_unsigned(1,1); end if; end if; end if; end if; end if; end if; -- This section generates the timer/counter overflow flag1 if tcon_tr1_i = '1' then if s_count_enable = '1' then if s_count0(15 downto 8) = conv_unsigned(255,8) then s_tf1 <= '1'; else s_tf1 <= '0'; end if; end if; end if; -- This section generates the high byte register of tmr/ctr0 if wt_i = "10" and wt_en_i = '1' then s_counth0 <= unsigned(reload_i); else if tcon_tr1_i = '1' then if s_count_enable = '1' then if s_counth0 = conv_unsigned(255,8) then s_counth0 <= conv_unsigned(0,8); else s_counth0 <= s_counth0 + conv_unsigned(1,1); end if; end if; end if; end if;⌨️ 快捷键说明
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