epm7064.qsf

网上流传的usb_blaster原理图里的CPLD源码,主要是实现usb时序转换成JATG时序输出！

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		jtag_cpld_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:12:05  JULY 18, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VHDL_FILE jtag_logic.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_43 -to CLK
set_location_assignment PIN_6 -to D[0]
set_location_assignment PIN_5 -to D[1]
set_location_assignment PIN_4 -to D[2]
set_location_assignment PIN_41 -to D[3]
set_location_assignment PIN_40 -to D[4]
set_location_assignment PIN_39 -to D[5]
set_location_assignment PIN_37 -to D[6]
set_location_assignment PIN_36 -to D[7]
set_location_assignment PIN_34 -to WR
set_location_assignment PIN_33 -to nRD
set_location_assignment PIN_29 -to nRXF
set_location_assignment PIN_31 -to nTXE
set_location_assignment PIN_9 -to B_TCK
set_location_assignment PIN_18 -to B_TDI
set_location_assignment PIN_2 -to B_TDO
set_location_assignment PIN_11 -to B_TMS

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name TOP_LEVEL_ENTITY jtag_logic

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM7064SLC44-10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Simulator Assignments
# =====================
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
set_global_assignment -name VECTOR_INPUT_SOURCE reset_test.vwf