disp256_guo_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.8 基于256点阵的汉字显示」· Verilog 代码 · 共 23 行

`timescale 1us/1us

module	DISP256_GUO_TEST;
   reg   CLK;
   wire  [15:0] ROW, COLUMN;	


   DISP256_GUO  DISP256_GUO ( CLK, ROW, COLUMN );
 
   always #1 CLK=~CLK;

   initial
      begin
        CLK=0;
        #35  $finish;                          
      end

endmodule