pulse_fre_s.v

基于Verilog-HDL的硬件电路的实现 9.4 脉冲频率的测量与显示 9.4.1 脉冲频率的测量原理 9.4.2 频率计的工作原理 9.4.3 频率测量模块的设计与实现

module  PULSE_FRE_S  (PULSE, CLK, RST, PH, P, DP, LD);
    input    PULSE;
    input    CLK, RST;
    output   PH;                   
    output   [3:0] DP;              
    output   [4:0] LD;              
    output   [3:0] P; 
    wire     [16:0] FRE;
    wire     [3:0] BW, BQ, BB, BS, BG;

    PULSE_FRE PULSE_FRE (CLK, PULSE, RST, FRE);
    BIN_BCD   BIN_BCD   (CLK, FRE, BW, BQ, BB, BS, BG );	
    LCD  LCD  (CLK, RST, BW, BQ, BB, BS, BG, PH, P, DP, LD);
endmodule


/**********  进行脉冲频率测量 **********/	
module PULSE_FRE (CLK, CLKX, RST, FRE);
    input   CLK, RST, CLKX;
    output  [16:0] FRE;
    reg     [16:0] FRE;
    reg     [16:0] OUT;
    reg     CNT_EN, LOAD;
    wire    CNT_CLR;

    always @ (posedge CLK or negedge RST)
       begin
         if (!RST)
           begin
             CNT_EN=0;
             LOAD=1;
           end
         else 
           begin
             CNT_EN=~CNT_EN;
             LOAD=~CNT_EN;
           end
        end

    assign CNT_CLR=~(~CLK&LOAD);

    always @(posedge CLKX or negedge CNT_CLR)
       begin
        if (!CNT_CLR)   
           OUT=0;
        else if (CNT_EN)
           begin
             if (OUT==99999)
                 OUT=99999;
	     else
                 OUT=OUT+1;
           end
       end

    always @(posedge LOAD)
       begin
          FRE=OUT;
       end

endmodule

/*************数制转换**********************/					
module BIN_BCD (CLK, A, BW, BQ, BB, BS, BG);		
    input CLK;
    input  [16:0]A;        
    output [3:0]BW, BQ, BB, BS, BG;        	
    reg    [3:0]BW, BQ, BB, BS, BG;      
  					
    integer I;
    reg  [19:0]TEMP;
    reg  [16:0]C;
						
    					
    always @ (posedge CLK)
     begin
       C=A;
       TEMP=0;

       for (I=1; I<17; I=I+1)
           begin
           {TEMP, C}={TEMP[18:0], C, 1'b0};
           if (TEMP[3:0]>4'b0100)
              begin
                TEMP[3:0]=TEMP[3:0]+3;
              end 
           if (TEMP[7:4]>4'b0100)
              begin
                TEMP[7:4]=TEMP[7:4]+3;
              end 
           if (TEMP[11:8]>4'b0100)
              begin
                TEMP[11:8]=TEMP[11:8]+3;
              end 
           if (TEMP[15:12]>4'b0100)
              begin
                TEMP[15:12]=TEMP[15:12]+3;
              end 
           if (TEMP[19:16]>4'b0100)
              begin
                TEMP[19:16]=TEMP[19:16]+3;
              end 
           {BW, BQ, BB,  BS, BG}={TEMP[18:0], A[0]};
           end
     end
  
endmodule


/******************LCD显示**********************/
module  LCD (CLK, CLR, NUMW, NUMQ, NUMB, NUMS, NUMG, PH, P, DP, LD);
    input    CLK, CLR;
    input    [3:0] NUMW, NUMQ, NUMB, NUMS, NUMG;
    output   PH;
    output   [3:0] DP;
    output   [4:0] LD;
    output   [3:0] P;
    reg      [4:0] LD;
    reg      [3:0] P;
    reg      [2:0]COUNT;

    assign  PH=CLK;
    assign  DP[3]=CLK; 
    assign  DP[2]=CLK; 
    assign  DP[1]=CLK; 
    assign  DP[0]=CLK; 
                 
  
    always @ (posedge CLK or negedge CLR)
         if (!CLR)
            COUNT<=0;
         else if (COUNT==5)
            COUNT<=1;
         else 
            COUNT<=COUNT+1;
    
    
    always @ (COUNT)
      begin
         case (COUNT)
           3'b001:begin
                     P=NUMW;
                     LD=5'b00001;
                  end
           3'b010:begin
                     P=NUMQ;
                     LD=5'b00010;
                  end
           3'b011:begin
                     P=NUMB;
                     LD=5'b00100;
                  end
           3'b100:begin
                     P=NUMS;
                     LD=5'b01000;
                  end
           3'b101:begin
                     P=NUMG;
                     LD=5'b10000;
                  end
        endcase           
     end
endmodule