key_scan.vhd

这是我用Xilnx公司的sparten3 FPGA开发板上

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:57:33 01/09/2007 
-- Design Name: 
-- Module Name:    key_scan - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity key_scan is
    Port ( clk          : in  STD_LOGIC;
           clk_key_1khz : in  STD_LOGIC;
           row          : in  STD_LOGIC_VECTOR (1 downto 0);
           key          : out  STD_LOGIC_VECTOR (7 downto 0);
           start_pause  : out  STD_LOGIC;
           reset        : out  STD_LOGIC);
end key_scan;

architecture Behavioral of key_scan is
  
  signal key_pressed           :std_logic;
  signal scan_cnt              :std_logic_vector(3 downto 0):="0000";
  signal st_paus,rst,key_valid :std_logic;

begin

process(clk,clk_key_1khz,key_pressed)
begin
  if falling_edge(clk)then
    if(key_pressed='1' and clk_key_1khz='1')then
	 scan_cnt<=scan_cnt+'1';
	 end if;
  end if;
end process;
   
   key<="11111110" when scan_cnt(3 downto 1)="000"else
        "11111101" when scan_cnt(3 downto 1)="001"else
		  "11111011" when scan_cnt(3 downto 1)="010"else
		  "11110111" when scan_cnt(3 downto 1)="011"else
		  "11101111" when scan_cnt(3 downto 1)="100"else
		  "11011111" when scan_cnt(3 downto 1)="101"else
		  "10111111" when scan_cnt(3 downto 1)="110"else
		  "01111111";
	key_pressed<=row(0) when scan_cnt(0)='0' else
	             row(1);

process(clk_key_1khz,clk,key_pressed)
	variable cnt:integer;
begin

  if key_pressed='1' then
  cnt:=400;
  elsif falling_edge(clk)then
	   if cnt/=0 then
	   cnt:=cnt-1;
	   end if;
  end if;
    if cnt=2 then
	 key_valid<='1';
   else
	 key_valid<='0';
	 end if; 
	
end process;

process(clk,scan_cnt)
begin
  if rising_edge(clk) then
    case scan_cnt is
	
	 when"0000"=>
	 st_paus<='1';
	 rst<='0';
	 when"0010"=>
	 st_paus<='0';
	 rst<='1';
	 when others=>
	 st_paus<='0';
	 rst<='0';
	 end case;
  end if;
end process;
start_pause <=not (st_paus and key_valid);
reset       <=not (rst and key_valid) ;


end Behavioral;