clk_div.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:39:01 12/27/2006 
-- Design Name: 
-- Module Name:    clk_div - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_div is
    Port ( clk            : in   STD_LOGIC;
           clk_key_1khz   : out  STD_LOGIC;
           clk_ctrl       : out  STD_LOGIC);
end clk_div;

architecture Behavioral of clk_div is
begin
	process(clk)
--		variable q1: integer range 25 downto 1        :=1;
		variable q2: integer range 5000 downto 1      :=1;
		variable q3: integer range 12500000 downto 1  :=1;
	begin
		if rising_edge(clk) then
--			if q1=25 then q1:=1;clk_key<='0';
--			elsif q1=24 then q1:=q1+1;clk_key<='1';
--			elsif q1=23 then q1:=q1+1;clk_key<='1';
--			else	q1:=q1+1;clk_key<='0';
--			end if;
--			
			if q2=5000 then q2:=1;clk_key_1khz<='0';
			elsif q2=4999 then q2:=q2+1;clk_key_1khz<='1';
			else q2:=q2+1;clk_key_1khz<='0';
			end if;
			
			if q3=12500000 then q3:=1;clk_ctrl<='0';
			elsif q3=12499999 then q3:=q3+1;clk_ctrl<='1';
			else	q3:=q3+1;clk_ctrl<='0';
			end if;
		else
			null;
		end if;
	end process;
	
end Behavioral;