ctrl.vhd

这是我用Xilnx公司的sparten3 FPGA开发板上

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:02:02 12/29/2006 
-- Design Name: 
-- Module Name:    ctrl - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ctrl is
    Port ( clk         : in  std_logic;
			  clk_ctrl    : in  STD_LOGIC;
           reset       : in  STD_LOGIC;
           start_pause : in  STD_LOGIC;
           display_en  : out  STD_LOGIC);
end ctrl;

architecture Behavioral of ctrl is
	signal enable:std_logic;
begin

	process(clk,reset,start_pause)
		begin
		if reset='0' then
			enable<='1';
		elsif falling_edge(start_pause) then
			enable<=not enable;
		end if;
	end process;

    display_en<=enable and clk_ctrl;
	 
end Behavioral;