top_7seg.vhd

这是我用Xilnx公司的sparten3 FPGA开发板上

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:13:49 12/27/2006 
-- Design Name: 
-- Module Name:    Top_7seg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Top_7seg is
    Port ( clk  : in  STD_LOGIC;
           row  : in  STD_LOGIC_VECTOR (1 downto 0);
           buff   : out  STD_LOGIC_VECTOR (7 downto 0);
           cs_all : out  STD_LOGIC_VECTOR (2 downto 0);
           seg    : out  STD_LOGIC_VECTOR (3 downto 0));
end Top_7seg;

architecture Behavioral of Top_7seg is

component clk_div
	port( clk           :  in  std_logic;
			clk_key_1khz  :  out std_logic;
			clk_ctrl      :  out std_logic
		  );
end component;

component key_scan
	port( clk          :  in   std_logic;
			clk_key_1khz :  in   std_logic;
			row	       :  in   std_logic_vector(1 downto 0);
			key          :  out  std_logic_vector(7 downto 0);
			start_pause  :  out  std_logic;
			reset        :  out  std_logic
		 );
end component;

component ctrl
	port( clk          :  in  std_logic;
		   clk_ctrl     :  in  std_logic;
			reset        :  in  std_logic;
			start_pause  :  in  std_logic;
			display_en   :  out std_logic
			);
end component;

component display
	port( 
			clk          :  in  std_logic;
			display_en   :  in  std_logic;
			reset        :  in  std_logic;
			data         :  out std_logic_vector(7 downto 0);
			seg          :  out std_logic_vector(3 downto 0);
			cs           :  out std_logic_vector(2 downto 0)
		 );
end component;


signal clk_key_1khz,clk_ctrl,start_pause,reset,display_en : std_logic;
signal key,data : std_logic_vector(7 downto 0);
signal timer    : std_logic_vector(4 downto 0);
signal cs       : std_logic_vector(2 downto 0);

begin

 u1 : clk_div   port map (clk,clk_key_1khz,clk_ctrl);
 u2 : key_scan  port map (clk,clk_key_1khz,row,key,start_pause,reset);
 u3 : ctrl      port map (clk,clk_ctrl,reset,start_pause,display_en);
 u4 : display   port map (clk,display_en,reset,data,seg,cs);

process(clk)
	begin
		if rising_edge(clk) then
		timer<=timer+'1';
			if timer(4)='1' then
				cs_all<=cs;
				buff<=data;
			else
				cs_all<="000";
				buff<=key;
			end if;
		end if;
		
end process;
	
end Behavioral;