fdiv.cr.mti

来自「用verilog编写适中分频器 并且还有测试程序」· MTI 代码 · 共 16 行

D:/exercise/fdivision/fdiv.v {1 {vlog -work work D:/exercise/fdivision/fdiv.v
Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
-- Compiling module fdivision

Top level modules:
	fdivision

} {} {}} D:/exercise/fdivision/fdivt.v {1 {vlog -work work D:/exercise/fdivision/fdivt.v
Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
-- Compiling module fdivt

Top level modules:
	fdivt

} {} {}}