fdivt.v

用verilog编写适中分频器 并且还有测试程序

`timescale 1ns/1ns
module fdivt;
reg F10M,reset;
wire Fcycle;

always #50 F10M=~F10M;

initial
 begin
     reset=1;
     F10M=0;
     #100 reset=0;
     #100 reset=1;
     #100000 $stop;
end

fdivision m(.reset(reset),.F10M(F10M),.Fcycle(Fcycle));
endmodule