transcript

用verilog编写适中分频器 并且还有测试程序

# Reading G:/Program Files/Modeltech_6.0/win32/../tcl/vsim/pref.tcl 
# reading G:\Program Files\Modeltech_6.0\win32/../modelsim.ini
# reading modelsim.ini
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "D:/exercise/fdivision/fdiv.mpf" 
# Loading project fdiv
# Compile of fdiv.v was successful.
# Compile of fdivt.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.fdivt
# vsim work.fdivt 
# Loading work.fdivt
# Loading work.fdivision
# ** Warning: (vsim-3009) [TSCALE] - Module 'fdivision' does not have a `timescale directive in effect, but previous modules do.
#         Region: /fdivt/m
add wave sim:/fdivt/*
run
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run -all
# Break at D:/exercise/fdivision/fdivt.v line 14
quit -sim
# Compile of fdiv.v was successful.
# Compile of fdivt.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.fdivt
# vsim work.fdivt 
# Loading work.fdivt
# Loading work.fdivision
# ** Warning: (vsim-3009) [TSCALE] - Module 'fdivision' does not have a `timescale directive in effect, but previous modules do.
#         Region: /fdivt/m
add wave sim:/fdivt/*
run
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run -all
# Break at D:/exercise/fdivision/fdivt.v line 14
# Compile of fdiv.v was successful.
# Compile of fdivt.v was successful.
# 2 compiles, 0 failed with no errors. 
# Compile of fdiv.v was successful.
# Compile of fdivt.v was successful.
# 2 compiles, 0 failed with no errors. 
add wave sim:/fdivt/*
add wave sim:/fdivt/*
quit -sim
# Compile of fdiv.v was successful.
# Compile of fdivt.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.fdivt
# vsim work.fdivt 
# Loading work.fdivt
# Loading work.fdivision
# ** Warning: (vsim-3009) [TSCALE] - Module 'fdivision' does not have a `timescale directive in effect, but previous modules do.
#         Region: /fdivt/m
add wave sim:/fdivt/*
run -all
# Break at D:/exercise/fdivision/fdivt.v line 14
# Compile of fdiv.v failed with 1 errors.
# Compile of fdivt.v was successful.
# 2 compiles, 1 failed with 1 error. 
# Compile of fdiv.v was successful.
# Compile of fdivt.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.fdivt
# vsim work.fdivt 
# Loading work.fdivt
# Loading work.fdivision
# ** Warning: (vsim-3009) [TSCALE] - Module 'fdivision' does not have a `timescale directive in effect, but previous modules do.
#         Region: /fdivt/m
add wave sim:/fdivt/*
run -all
# Break at D:/exercise/fdivision/fdivt.v line 14
quit -sim
# reading modelsim.ini
# reading G:\Program Files\Modeltech_6.0\win32/../modelsim.ini
# Loading project block