fdiv.v

用verilog编写适中分频器 并且还有测试程序

module fdivision(reset,F10M,Fcycle);
    input reset,F10M;
    output Fcycle;
    reg Fcycle;
    reg[0:8] j;
    always @(posedge F10M)
       if(!reset) 
          begin
             Fcycle<=0;
            
             j<=0; 
          end
        else
           begin
               if(j==199)
                  begin
                     Fcycle<=~Fcycle;
                   j<=j+1;
                    
                   end
               
              else if(j==299)
                 begin
                    
                    Fcycle<=~Fcycle;
                     
                     j<=0;
                 end
             else
                j<=j+1;    
            end
endmodule