half_clkt.v

用verilog编写适中分频器 并且还有测试程序

`timescale 1ns/100ps
module half_clkt;
reg clk,reset;
wire clk_out;

always #100 clk =~clk;

initial
 begin
    clk=0;
    reset=1;
 #10 reset=0;
 #110 reset=1;
 #100000 $stop;
 end
 
half_clk n0(.reset(reset),.clk_in(clk),.clk_out(clk_out));

endmodule