transcript

用verilog编写适中分频器 并且还有测试程序

# Reading G:/Program Files/Modeltech_6.0/win32/../tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "D:/exercise/half_clk/half_clk.mpf" 
# Loading project half_clk
vsim work.half_clkt
# vsim work.half_clkt 
# Loading work.half_clkt
# Loading work.half_clk
# ** Warning: (vsim-3009) [TSCALE] - Module 'half_clk' does not have a `timescale directive in effect, but previous modules do.
#         Region: /half_clkt/n0
add wave sim:/half_clkt/*
run -all
# Break at D:/exercise/half_clk/half_clkt.v line 14
quit -sim
# reading G:\Program Files\Modeltech_6.0\win32/../modelsim.ini
# Loading project block
# Compile of compareTop.v was successful.
# Compile of blocking.v was successful.
# Compile of non_blocking.v was successful.
# 3 compiles, 0 failed with no errors. 
vsim work.compareTop
# vsim work.compareTop 
# Loading work.compareTop
# Loading work.blocking
# ** Warning: (vsim-3009) [TSCALE] - Module 'blocking' does not have a `timescale directive in effect, but previous modules do.
#         Region: /compareTop/n
add wave sim:/compareTop/*
run -all
# Blocking:a= 3,b= 3,c= 3.
# Blocking:a= 7,b= 7,c= 7.
# Blocking:a= 7,b= 7,c= 7.
# Blocking:a= 7,b= 7,c= 7.
# Blocking:a= 7,b= 7,c= 7.
# Break at D:/exercise/blocking/compareTop.v line 26
quit -sim
# Compile of non_blocking.v was successful.
# Compile of compareTop.v failed with 1 errors.
# Compile of blocking.v failed with 1 errors.
# Compile of non_blocking.v was successful.
# 3 compiles, 2 failed with 2 errors. 
# Compile of blocking.v was successful.
# Compile of compareTop.v was successful.
vsim work.compareTop
# vsim work.compareTop 
# Loading work.compareTop
# Loading work.blocking
add wave sim:/compareTop/*
run -all
# Break at D:/exercise/blocking/compareTop.v line 26
quit -sim
# Compile of compareTop.v was successful.
# Compile of blocking.v was successful.
# Compile of non_blocking.v was successful.
# 3 compiles, 0 failed with no errors. 
vsim work.compareTop
# vsim work.compareTop 
# Loading work.compareTop
# Loading work.blocking
# ** Warning: (vsim-3009) [TSCALE] - Module 'blocking' does not have a `timescale directive in effect, but previous modules do.
#         Region: /compareTop/n
add wave sim:/compareTop/*
run -all
# Blocking:a= 3,b= 3,c= 3.
# Blocking:a= 7,b= 7,c= 7.
# Blocking:a= 7,b= 7,c= 7.
# Blocking:a= 7,b= 7,c= 7.
# Blocking:a= 7,b= 7,c= 7.
# Break at D:/exercise/blocking/compareTop.v line 26
quit -sim
# Compile of non_blocking.v was successful.
# Compile of compareTop.v was successful.
# Compile of blocking.v was successful.
# Compile of non_blocking.v was successful.
# 3 compiles, 0 failed with no errors. 
vsim work.compareTop
# vsim work.compareTop 
# Loading work.compareTop
# Loading work.non_blocking
# ** Warning: (vsim-3009) [TSCALE] - Module 'non_blocking' does not have a `timescale directive in effect, but previous modules do.
#         Region: /compareTop/m
# Loading work.blocking
# ** Warning: (vsim-3009) [TSCALE] - Module 'blocking' does not have a `timescale directive in effect, but previous modules do.
#         Region: /compareTop/n
add wave sim:/compareTop/*
run -all
# Blocking:a= 3,b= 3,c= 3.
# Non_blocking:a= 3,b= x,c= x.
# Blocking:a= 7,b= 7,c= 7.
# Non_blocking:a= 7,b= 3,c= x.
# Blocking:a= 7,b= 7,c= 7.
# Non_blocking:a= 7,b= 7,c= 3.
# Blocking:a= 7,b= 7,c= 7.
# Non_blocking:a= 7,b= 7,c= 7.
# Blocking:a= 7,b= 7,c= 7.
# Non_blocking:a= 7,b= 7,c= 7.
# Break at D:/exercise/blocking/compareTop.v line 26
quit -sim
# reading G:\Program Files\Modeltech_6.0\win32/../modelsim.ini
# Loading project select
cd D:/exercise/select
# reading G:\Program Files\Modeltech_6.0\win32/../modelsim.ini
# Loading project select