half_clk.cr.mti

用verilog编写适中分频器 并且还有测试程序

D:/exercise/half_clk/half_clk.v {1 {vlog -work work D:/exercise/half_clk/half_clk.v
Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
-- Compiling module half_clk

Top level modules:
	half_clk

} {} {}} D:/exercise/half_clk/half_clkt.v {1 {vlog -work work D:/exercise/half_clk/half_clkt.v
Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
-- Compiling module half_clkt

Top level modules:
	half_clkt

} {} {}}