comparetop.v

基于verilog语言的数据选择器

`timescale 1ns/100ps
`include "./blocking.v"

//`include "./non_blocking.v"

module compareTop;
    
    wire[3:0]b1,c1,d,e,b2,c2;
    reg[3:0]a;
    reg clk;
    
    initial
    begin
        clk=0;
        forever #50 clk=~clk;
    end
    
    initial 
    begin
        a=4'h3;
        #100 a=4'h7;
        #100 a=4'h7;
        #100 a=4'h7;
        #100 a=4'h7;
        #100 ;
        $stop; 
    end
    non_blocking m(clk,a,b2,c2);
    blocking     n(clk,a,b1,c1,d,e);
   
endmodule