dds_vhdl.map.eqn

数字移相信号发生器设计

RB2_q_a[8]_PORT_A_data_in = VCC;
RB2_q_a[8]_PORT_A_data_in_reg = DFFE(RB2_q_a[8]_PORT_A_data_in, RB2_q_a[8]_clock_0, , , );
RB2_q_a[8]_PORT_B_data_in = SB2_ram_rom_data_reg[8];
RB2_q_a[8]_PORT_B_data_in_reg = DFFE(RB2_q_a[8]_PORT_B_data_in, RB2_q_a[8]_clock_1, , , );
RB2_q_a[8]_PORT_A_address = BUS(E1_DOUT[22], E1_DOUT[23], E1_DOUT[24], E1_DOUT[25], E1_DOUT[26], E1_DOUT[27], E1_DOUT[28], E1_DOUT[29], E1_DOUT[30], E1_DOUT[31]);
RB2_q_a[8]_PORT_A_address_reg = DFFE(RB2_q_a[8]_PORT_A_address, RB2_q_a[8]_clock_0, , , );
RB2_q_a[8]_PORT_B_address = BUS(TB2_safe_q[0], TB2_safe_q[1], TB2_safe_q[2], TB2_safe_q[3], TB2_safe_q[4], TB2_safe_q[5], TB2_safe_q[6], TB2_safe_q[7], TB2_safe_q[8], TB2_safe_q[9]);
RB2_q_a[8]_PORT_B_address_reg = DFFE(RB2_q_a[8]_PORT_B_address, RB2_q_a[8]_clock_1, , , );
RB2_q_a[8]_PORT_A_write_enable = GND;
RB2_q_a[8]_PORT_A_write_enable_reg = DFFE(RB2_q_a[8]_PORT_A_write_enable, RB2_q_a[8]_clock_0, , , );
RB2_q_a[8]_PORT_B_write_enable = SB2L62;
RB2_q_a[8]_PORT_B_write_enable_reg = DFFE(RB2_q_a[8]_PORT_B_write_enable, RB2_q_a[8]_clock_1, , , );
RB2_q_a[8]_clock_0 = CLK;
RB2_q_a[8]_clock_1 = A1L5;
RB2_q_a[8]_PORT_A_data_out = MEMORY(RB2_q_a[8]_PORT_A_data_in_reg, RB2_q_a[8]_PORT_B_data_in_reg, RB2_q_a[8]_PORT_A_address_reg, RB2_q_a[8]_PORT_B_address_reg, RB2_q_a[8]_PORT_A_write_enable_reg, RB2_q_a[8]_PORT_B_write_enable_reg, , , RB2_q_a[8]_clock_0, RB2_q_a[8]_clock_1, , , , );
RB2_q_a[8] = RB2_q_a[8]_PORT_A_data_out[0];

--RB2_q_b[8] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[8]
RB2_q_b[8]_PORT_A_data_in = VCC;
RB2_q_b[8]_PORT_A_data_in_reg = DFFE(RB2_q_b[8]_PORT_A_data_in, RB2_q_b[8]_clock_0, , , );
RB2_q_b[8]_PORT_B_data_in = SB2_ram_rom_data_reg[8];
RB2_q_b[8]_PORT_B_data_in_reg = DFFE(RB2_q_b[8]_PORT_B_data_in, RB2_q_b[8]_clock_1, , , );
RB2_q_b[8]_PORT_A_address = BUS(E1_DOUT[22], E1_DOUT[23], E1_DOUT[24], E1_DOUT[25], E1_DOUT[26], E1_DOUT[27], E1_DOUT[28], E1_DOUT[29], E1_DOUT[30], E1_DOUT[31]);
RB2_q_b[8]_PORT_A_address_reg = DFFE(RB2_q_b[8]_PORT_A_address, RB2_q_b[8]_clock_0, , , );
RB2_q_b[8]_PORT_B_address = BUS(TB2_safe_q[0], TB2_safe_q[1], TB2_safe_q[2], TB2_safe_q[3], TB2_safe_q[4], TB2_safe_q[5], TB2_safe_q[6], TB2_safe_q[7], TB2_safe_q[8], TB2_safe_q[9]);
RB2_q_b[8]_PORT_B_address_reg = DFFE(RB2_q_b[8]_PORT_B_address, RB2_q_b[8]_clock_1, , , );
RB2_q_b[8]_PORT_A_write_enable = GND;
RB2_q_b[8]_PORT_A_write_enable_reg = DFFE(RB2_q_b[8]_PORT_A_write_enable, RB2_q_b[8]_clock_0, , , );
RB2_q_b[8]_PORT_B_write_enable = SB2L62;
RB2_q_b[8]_PORT_B_write_enable_reg = DFFE(RB2_q_b[8]_PORT_B_write_enable, RB2_q_b[8]_clock_1, , , );
RB2_q_b[8]_clock_0 = CLK;
RB2_q_b[8]_clock_1 = A1L5;
RB2_q_b[8]_PORT_B_data_out = MEMORY(RB2_q_b[8]_PORT_A_data_in_reg, RB2_q_b[8]_PORT_B_data_in_reg, RB2_q_b[8]_PORT_A_address_reg, RB2_q_b[8]_PORT_B_address_reg, RB2_q_b[8]_PORT_A_write_enable_reg, RB2_q_b[8]_PORT_B_write_enable_reg, , , RB2_q_b[8]_clock_0, RB2_q_b[8]_clock_1, , , , );
RB2_q_b[8] = RB2_q_b[8]_PORT_B_data_out[0];


--RB2_q_a[7] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB2_q_a[7]_PORT_A_data_in = VCC;
RB2_q_a[7]_PORT_A_data_in_reg = DFFE(RB2_q_a[7]_PORT_A_data_in, RB2_q_a[7]_clock_0, , , );
RB2_q_a[7]_PORT_B_data_in = SB2_ram_rom_data_reg[7];
RB2_q_a[7]_PORT_B_data_in_reg = DFFE(RB2_q_a[7]_PORT_B_data_in, RB2_q_a[7]_clock_1, , , );
RB2_q_a[7]_PORT_A_address = BUS(E1_DOUT[22], E1_DOUT[23], E1_DOUT[24], E1_DOUT[25], E1_DOUT[26], E1_DOUT[27], E1_DOUT[28], E1_DOUT[29], E1_DOUT[30], E1_DOUT[31]);
RB2_q_a[7]_PORT_A_address_reg = DFFE(RB2_q_a[7]_PORT_A_address, RB2_q_a[7]_clock_0, , , );
RB2_q_a[7]_PORT_B_address = BUS(TB2_safe_q[0], TB2_safe_q[1], TB2_safe_q[2], TB2_safe_q[3], TB2_safe_q[4], TB2_safe_q[5], TB2_safe_q[6], TB2_safe_q[7], TB2_safe_q[8], TB2_safe_q[9]);
RB2_q_a[7]_PORT_B_address_reg = DFFE(RB2_q_a[7]_PORT_B_address, RB2_q_a[7]_clock_1, , , );
RB2_q_a[7]_PORT_A_write_enable = GND;
RB2_q_a[7]_PORT_A_write_enable_reg = DFFE(RB2_q_a[7]_PORT_A_write_enable, RB2_q_a[7]_clock_0, , , );
RB2_q_a[7]_PORT_B_write_enable = SB2L62;
RB2_q_a[7]_PORT_B_write_enable_reg = DFFE(RB2_q_a[7]_PORT_B_write_enable, RB2_q_a[7]_clock_1, , , );
RB2_q_a[7]_clock_0 = CLK;
RB2_q_a[7]_clock_1 = A1L5;
RB2_q_a[7]_PORT_A_data_out = MEMORY(RB2_q_a[7]_PORT_A_data_in_reg, RB2_q_a[7]_PORT_B_data_in_reg, RB2_q_a[7]_PORT_A_address_reg, RB2_q_a[7]_PORT_B_address_reg, RB2_q_a[7]_PORT_A_write_enable_reg, RB2_q_a[7]_PORT_B_write_enable_reg, , , RB2_q_a[7]_clock_0, RB2_q_a[7]_clock_1, , , , );
RB2_q_a[7] = RB2_q_a[7]_PORT_A_data_out[0];

--RB2_q_b[7] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[7]
RB2_q_b[7]_PORT_A_data_in = VCC;
RB2_q_b[7]_PORT_A_data_in_reg = DFFE(RB2_q_b[7]_PORT_A_data_in, RB2_q_b[7]_clock_0, , , );
RB2_q_b[7]_PORT_B_data_in = SB2_ram_rom_data_reg[7];
RB2_q_b[7]_PORT_B_data_in_reg = DFFE(RB2_q_b[7]_PORT_B_data_in, RB2_q_b[7]_clock_1, , , );
RB2_q_b[7]_PORT_A_address = BUS(E1_DOUT[22], E1_DOUT[23], E1_DOUT[24], E1_DOUT[25], E1_DOUT[26], E1_DOUT[27], E1_DOUT[28], E1_DOUT[29], E1_DOUT[30], E1_DOUT[31]);
RB2_q_b[7]_PORT_A_address_reg = DFFE(RB2_q_b[7]_PORT_A_address, RB2_q_b[7]_clock_0, , , );
RB2_q_b[7]_PORT_B_address = BUS(TB2_safe_q[0], TB2_safe_q[1], TB2_safe_q[2], TB2_safe_q[3], TB2_safe_q[4], TB2_safe_q[5], TB2_safe_q[6], TB2_safe_q[7], TB2_safe_q[8], TB2_safe_q[9]);
RB2_q_b[7]_PORT_B_address_reg = DFFE(RB2_q_b[7]_PORT_B_address, RB2_q_b[7]_clock_1, , , );
RB2_q_b[7]_PORT_A_write_enable = GND;
RB2_q_b[7]_PORT_A_write_enable_reg = DFFE(RB2_q_b[7]_PORT_A_write_enable, RB2_q_b[7]_clock_0, , , );
RB2_q_b[7]_PORT_B_write_enable = SB2L62;
RB2_q_b[7]_PORT_B_write_enable_reg = DFFE(RB2_q_b[7]_PORT_B_write_enable, RB2_q_b[7]_clock_1, , , );
RB2_q_b[7]_clock_0 = CLK;
RB2_q_b[7]_clock_1 = A1L5;
RB2_q_b[7]_PORT_B_data_out = MEMORY(RB2_q_b[7]_PORT_A_data_in_reg, RB2_q_b[7]_PORT_B_data_in_reg, RB2_q_b[7]_PORT_A_address_reg, RB2_q_b[7]_PORT_B_address_reg, RB2_q_b[7]_PORT_A_write_enable_reg, RB2_q_b[7]_PORT_B_write_enable_reg, , , RB2_q_b[7]_clock_0, RB2_q_b[7]_clock_1, , , , );
RB2_q_b[7] = RB2_q_b[7]_PORT_B_data_out[0];


--RB2_q_a[6] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB2_q_a[6]_PORT_A_data_in = VCC;
RB2_q_a[6]_PORT_A_data_in_reg = DFFE(RB2_q_a[6]_PORT_A_data_in, RB2_q_a[6]_clock_0, , , );
RB2_q_a[6]_PORT_B_data_in = SB2_ram_rom_data_reg[6];
RB2_q_a[6]_PORT_B_data_in_reg = DFFE(RB2_q_a[6]_PORT_B_data_in, RB2_q_a[6]_clock_1, , , );
RB2_q_a[6]_PORT_A_address = BUS(E1_DOUT[22], E1_DOUT[23], E1_DOUT[24], E1_DOUT[25], E1_DOUT[26], E1_DOUT[27], E1_DOUT[28], E1_DOUT[29], E1_DOUT[30], E1_DOUT[31]);
RB2_q_a[6]_PORT_A_address_reg = DFFE(RB2_q_a[6]_PORT_A_address, RB2_q_a[6]_clock_0, , , );
RB2_q_a[6]_PORT_B_address = BUS(TB2_safe_q[0], TB2_safe_q[1], TB2_safe_q[2], TB2_safe_q[3], TB2_safe_q[4], TB2_safe_q[5], TB2_safe_q[6], TB2_safe_q[7], TB2_safe_q[8], TB2_safe_q[9]);
RB2_q_a[6]_PORT_B_address_reg = DFFE(RB2_q_a[6]_PORT_B_address, RB2_q_a[6]_clock_1, , , );
RB2_q_a[6]_PORT_A_write_enable = GND;
RB2_q_a[6]_PORT_A_write_enable_reg = DFFE(RB2_q_a[6]_PORT_A_write_enable, RB2_q_a[6]_clock_0, , , );
RB2_q_a[6]_PORT_B_write_enable = SB2L62;
RB2_q_a[6]_PORT_B_write_enable_reg = DFFE(RB2_q_a[6]_PORT_B_write_enable, RB2_q_a[6]_clock_1, , , );
RB2_q_a[6]_clock_0 = CLK;
RB2_q_a[6]_clock_1 = A1L5;
RB2_q_a[6]_PORT_A_data_out = MEMORY(RB2_q_a[6]_PORT_A_data_in_reg, RB2_q_a[6]_PORT_B_data_in_reg, RB2_q_a[6]_PORT_A_address_reg, RB2_q_a[6]_PORT_B_address_reg, RB2_q_a[6]_PORT_A_write_enable_reg, RB2_q_a[6]_PORT_B_write_enable_reg, , , RB2_q_a[6]_clock_0, RB2_q_a[6]_clock_1, , , , );
RB2_q_a[6] = RB2_q_a[6]_PORT_A_data_out[0];

--RB2_q_b[6] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[6]
RB2_q_b[6]_PORT_A_data_in = VCC;
RB2_q_b[6]_PORT_A_data_in_reg = DFFE(RB2_q_b[6]_PORT_A_data_in, RB2_q_b[6]_clock_0, , , );
RB2_q_b[6]_PORT_B_data_in = SB2_ram_rom_data_reg[6];
RB2_q_b[6]_PORT_B_data_in_reg = DFFE(RB2_q_b[6]_PORT_B_data_in, RB2_q_b[6]_clock_1, , , );
RB2_q_b[6]_PORT_A_address = BUS(E1_DOUT[22], E1_DOUT[23], E1_DOUT[24], E1_DOUT[25], E1_DOUT[26], E1_DOUT[27], E1_DOUT[28], E1_DOUT[29], E1_DOUT[30], E1_DOUT[31]);
RB2_q_b[6]_PORT_A_address_reg = DFFE(RB2_q_b[6]_PORT_A_address, RB2_q_b[6]_clock_0, , , );
RB2_q_b[6]_PORT_B_address = BUS(TB2_safe_q[0], TB2_safe_q[1], TB2_safe_q[2], TB2_safe_q[3], TB2_safe_q[4], TB2_safe_q[5], TB2_safe_q[6], TB2_safe_q[7], TB2_safe_q[8], TB2_safe_q[9]);
RB2_q_b[6]_PORT_B_address_reg = DFFE(RB2_q_b[6]_PORT_B_address, RB2_q_b[6]_clock_1, , , );
RB2_q_b[6]_PORT_A_write_enable = GND;
RB2_q_b[6]_PORT_A_write_enable_reg = DFFE(RB2_q_b[6]_PORT_A_write_enable, RB2_q_b[6]_clock_0, , , );
RB2_q_b[6]_PORT_B_write_enable = SB2L62;
RB2_q_b[6]_PORT_B_write_enable_reg = DFFE(RB2_q_b[6]_PORT_B_write_enable, RB2_q_b[6]_clock_1, , , );
RB2_q_b[6]_clock_0 = CLK;
RB2_q_b[6]_clock_1 = A1L5;
RB2_q_b[6]_PORT_B_data_out = MEMORY(RB2_q_b[6]_PORT_A_data_in_reg, RB2_q_b[6]_PORT_B_data_in_reg, RB2_q_b[6]_PORT_A_address_reg, RB2_q_b[6]_PORT_B_address_reg, RB2_q_b[6]_PORT_A_write_enable_reg, RB2_q_b[6]_PORT_B_write_enable_reg, , , RB2_q_b[6]_clock_0, RB2_q_b[6]_clock_1, , , , );
RB2_q_b[6] = RB2_q_b[6]_PORT_B_data_out[0];


--RB2_q_a[5] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB2_q_a[5]_PORT_A_data_in = VCC;
RB2_q_a[5]_PORT_A_data_in_reg = DFFE(RB2_q_a[5]_PORT_A_data_in, RB2_q_a[5]_clock_0, , , );
RB2_q_a[5]_PORT_B_data_in = SB2_ram_rom_data_reg[5];
RB2_q_a[5]_PORT_B_data_in_reg = DFFE(RB2_q_a[5]_PORT_B_data_in, RB2_q_a[5]_clock_1, , , );
RB2_q_a[5]_PORT_A_address = BUS(E1_DOUT[22], E1_DOUT[23], E1_DOUT[24], E1_DOUT[25], E1_DOUT[26], E1_DOUT[27], E1_DOUT[28], E1_DOUT[29], E1_DOUT[30], E1_DOUT[31]);
RB2_q_a[5]_PORT_A_address_reg = DFFE(RB2_q_a[5]_PORT_A_address, RB2_q_a[5]_clock_0, , , );
RB2_q_a[5]_PORT_B_address = BUS(TB2_safe_q[0], TB2_safe_q[1], TB2_safe_q[2], TB2_safe_q[3], TB2_safe_q[4], TB2_safe_q[5], TB2_safe_q[6], TB2_safe_q[7], TB2_safe_q[8], TB2_safe_q[9]);
RB2_q_a[5]_PORT_B_address_reg = DFFE(RB2_q_a[5]_PORT_B_address, RB2_q_a[5]_clock_1, , , );
RB2_q_a[5]_PORT_A_write_enable = GND;
RB2_q_a[5]_PORT_A_write_enable_reg = DFFE(RB2_q_a[5]_PORT_A_write_enable, RB2_q_a[5]_clock_0, , , );
RB2_q_a[5]_PORT_B_write_enable = SB2L62;
RB2_q_a[5]_PORT_B_write_enable_reg = DFFE(RB2_q_a[5]_PORT_B_write_enable, RB2_q_a[5]_clock_1, , , );
RB2_q_a[5]_clock_0 = CLK;
RB2_q_a[5]_clock_1 = A1L5;
RB2_q_a[5]_PORT_A_data_out = MEMORY(RB2_q_a[5]_PORT_A_data_in_reg, RB2_q_a[5]_PORT_B_data_in_reg, RB2_q_a[5]_PORT_A_address_reg, RB2_q_a[5]_PORT_B_address_reg, RB2_q_a[5]_PORT_A_write_enable_reg, RB2_q_a[5]_PORT_B_write_enable_reg, , , RB2_q_a[5]_clock_0, RB2_q_a[5]_clock_1, , , , );
RB2_q_a[5] = RB2_q_a[5]_PORT_A_data_out[0];

--RB2_q_b[5] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[5]
RB2_q_b[5]_PORT_A_data_in = VCC;
RB2_q_b[5]_PORT_A_data_in_reg = DFFE(RB2_q_b[5]_PORT_A_data_in, RB2_q_b[5]_clock_0, , , );
RB2_q_b[5]_PORT_B_data_in = SB2_ram_rom_data_reg[5];
RB2_q_b[5]_PORT_B_data_in_reg = DFFE(RB2_q_b[5]_PORT_B_data_in, RB2_q_b[5]_clock_1, , , );
RB2_q_b[5]_PORT_A_address = BUS(E1_DOUT[22], E1_DOUT[23], E1_DOUT[24], E1_DOUT[25], E1_DOUT[26], E1_DOUT[27], E1_DOUT[28], E1_DOUT[29], E1_DOUT[30], E1_DOUT[31]);
RB2_q_b[5]_PORT_A_address_reg = DFFE(RB2_q_b[5]_PORT_A_address, RB2_q_b[5]_clock_0, , , );
RB2_q_b[5]_PORT_B_address = BUS(TB2_safe_q[0], TB2_safe_q[1], TB2_safe_q[2], TB2_safe_q[3], TB2_safe_q[4], TB2_safe_q[5], TB2_safe_q[6], TB2_safe_q[7], TB2_safe_q[8], TB2_safe_q[9]);
RB2_q_b[5]_PORT_B_address_reg = DFFE(RB2_q_b[5]_PORT_B_address, RB2_q_b[5]_clock_1, , , );
RB2_q_b[5]_PORT_A_write_enable = GND;
RB2_q_b[5]_PORT_A_write_enable_reg = DFFE(RB2_q_b[5]_PORT_A_write_enable, RB2_q_b[5]_clock_0, , , );
RB2_q_b[5]_PORT_B_write_enable = SB2L62;