dds_vhdl.fit.qmsg

数字移相信号发生器设计

{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "3 " "Info: Fitter placement preparation operations ending: elapsed time = 3 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.526 ns register register " "Info: Estimated most critical path is register to register delay of 3.526 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:phase\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] 1 REG LAB_X13_Y14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y14; Fanout = 1; REG Node = 'sld_signaltap:phase\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.263 ns) + CELL(0.114 ns) 1.377 ns sld_hub:sld_hub_inst\|HUB_TDO~818 2 COMB LAB_X14_Y13 1 " "Info: 2: + IC(1.263 ns) + CELL(0.114 ns) = 1.377 ns; Loc. = LAB_X14_Y13; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~818'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.377 ns" { sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~818 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.219 ns) + CELL(0.590 ns) 2.186 ns sld_hub:sld_hub_inst\|HUB_TDO~819 3 COMB LAB_X15_Y13 1 " "Info: 3: + IC(0.219 ns) + CELL(0.590 ns) = 2.186 ns; Loc. = LAB_X15_Y13; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~819'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.809 ns" { sld_hub:sld_hub_inst|HUB_TDO~818 sld_hub:sld_hub_inst|HUB_TDO~819 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.292 ns) 2.763 ns sld_hub:sld_hub_inst\|HUB_TDO~820 4 COMB LAB_X15_Y13 1 " "Info: 4: + IC(0.285 ns) + CELL(0.292 ns) = 2.763 ns; Loc. = LAB_X15_Y13; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~820'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.577 ns" { sld_hub:sld_hub_inst|HUB_TDO~819 sld_hub:sld_hub_inst|HUB_TDO~820 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.478 ns) 3.526 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 5 REG LAB_X15_Y13 0 " "Info: 5: + IC(0.285 ns) + CELL(0.478 ns) = 3.526 ns; Loc. = LAB_X15_Y13; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.763 ns" { sld_hub:sld_hub_inst|HUB_TDO~820 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.474 ns 41.80 % " "Info: Total cell delay = 1.474 ns ( 41.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.052 ns 58.20 % " "Info: Total interconnect delay = 2.052 ns ( 58.20 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "3.526 ns" { sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~818 sld_hub:sld_hub_inst|HUB_TDO~819 sld_hub:sld_hub_inst|HUB_TDO~820 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Info: Estimated interconnect usage is 6% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "3 " "Info: Fitter placement operations ending: elapsed time = 3 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "4 " "Info: Fitter routing operations ending: elapsed time = 4 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] -- routed using non-global resources" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] -- routed using non-global resources" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] -- routed using non-global resources" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] -- routed using non-global resources" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { Floorplan "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 16:07:26 2005 " "Info: Processing ended: Wed Dec 14 16:07:26 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Info: Elapsed time: 00:00:29" {  } {  } 0}  } {  } 0}