dds_vhdl.tan.qmsg

数字移相信号发生器设计

{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[2\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 2.827 ns register " "Info: th for register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[2\] (data pin = altera_internal_jtag~TMSUTAP, clock pin = altera_internal_jtag~TCKUTAP) is 2.827 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.908 ns + Longest register " "Info: + Longest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 535 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 535; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.197 ns) + CELL(0.711 ns) 4.908 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[2\] 2 REG LC_X12_Y12_N5 2 " "Info: 2: + IC(4.197 ns) + CELL(0.711 ns) = 4.908 ns; Loc. = LC_X12_Y12_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[2\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.908 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.49 % " "Info: Total cell delay = 0.711 ns ( 14.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.197 ns 85.51 % " "Info: Total interconnect delay = 4.197 ns ( 85.51 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.908 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.096 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.096 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y10_N1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.618 ns) + CELL(0.478 ns) 2.096 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[2\] 2 REG LC_X12_Y12_N5 2 " "Info: 2: + IC(1.618 ns) + CELL(0.478 ns) = 2.096 ns; Loc. = LC_X12_Y12_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[2\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.096 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 22.81 % " "Info: Total cell delay = 0.478 ns ( 22.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.618 ns 77.19 % " "Info: Total interconnect delay = 1.618 ns ( 77.19 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.096 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.908 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.096 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK POUT\[2\] sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a9~porta_address_reg9 12.609 ns memory " "Info: Minimum tco from clock CLK to destination pin POUT\[2\] through memory sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a9~porta_address_reg9 is 12.609 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.900 ns + Shortest memory " "Info: + Shortest clock path from clock CLK to source memory is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 449 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 449; CLK Node = 'CLK'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.722 ns) 2.900 ns sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a9~porta_address_reg9 2 MEM M4K_X17_Y7 4 " "Info: 2: + IC(0.709 ns) + CELL(0.722 ns) = 2.900 ns; Loc. = M4K_X17_Y7; Fanout = 4; MEM Node = 'sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a9~porta_address_reg9'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.431 ns" { CLK sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg9 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" 331 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 75.55 % " "Info: Total cell delay = 2.191 ns ( 75.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.709 ns 24.45 % " "Info: Total interconnect delay = 0.709 ns ( 24.45 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.900 ns" { CLK sin_r