📄 dds_vhdl.tan.qmsg
字号:
{ "Info" "ITDB_TSU_RESULT" "REG10B:u5\|DOUT\[7\] PWORD\[1\] CLK 7.366 ns register " "Info: tsu for register REG10B:u5\|DOUT\[7\] (data pin = PWORD\[1\], clock pin = CLK) is 7.366 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.260 ns + Longest pin register " "Info: + Longest pin to register delay is 10.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PWORD\[1\] 1 PIN PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; PIN Node = 'PWORD\[1\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[1] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.054 ns) + CELL(0.564 ns) 9.087 ns REG10B:u5\|DOUT\[3\]~COUT0 2 COMB LC_X16_Y16_N1 2 " "Info: 2: + IC(7.054 ns) + CELL(0.564 ns) = 9.087 ns; Loc. = LC_X16_Y16_N1; Fanout = 2; COMB Node = 'REG10B:u5\|DOUT\[3\]~COUT0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "7.618 ns" { PWORD[1] REG10B:u5|DOUT[3]~COUT0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 9.165 ns REG10B:u5\|DOUT\[4\]~COUT0 3 COMB LC_X16_Y16_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 9.165 ns; Loc. = LC_X16_Y16_N2; Fanout = 2; COMB Node = 'REG10B:u5\|DOUT\[4\]~COUT0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.078 ns" { REG10B:u5|DOUT[3]~COUT0 REG10B:u5|DOUT[4]~COUT0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 9.243 ns REG10B:u5\|DOUT\[5\]~COUT0 4 COMB LC_X16_Y16_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 9.243 ns; Loc. = LC_X16_Y16_N3; Fanout = 2; COMB Node = 'REG10B:u5\|DOUT\[5\]~COUT0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.078 ns" { REG10B:u5|DOUT[4]~COUT0 REG10B:u5|DOUT[5]~COUT0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 9.421 ns REG10B:u5\|DOUT\[6\]~COUT 5 COMB LC_X16_Y16_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 9.421 ns; Loc. = LC_X16_Y16_N4; Fanout = 3; COMB Node = 'REG10B:u5\|DOUT\[6\]~COUT'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.178 ns" { REG10B:u5|DOUT[5]~COUT0 REG10B:u5|DOUT[6]~COUT } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 10.260 ns REG10B:u5\|DOUT\[7\] 6 REG LC_X16_Y16_N5 3 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 10.260 ns; Loc. = LC_X16_Y16_N5; Fanout = 3; REG Node = 'REG10B:u5\|DOUT\[7\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.839 ns" { REG10B:u5|DOUT[6]~COUT REG10B:u5|DOUT[7] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.206 ns 31.25 % " "Info: Total cell delay = 3.206 ns ( 31.25 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.054 ns 68.75 % " "Info: Total interconnect delay = 7.054 ns ( 68.75 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "10.260 ns" { PWORD[1] REG10B:u5|DOUT[3]~COUT0 REG10B:u5|DOUT[4]~COUT0 REG10B:u5|DOUT[5]~COUT0 REG10B:u5|DOUT[6]~COUT REG10B:u5|DOUT[7] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.931 ns - Shortest register " "Info: - Shortest clock path from clock CLK to destination register is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 449 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 449; CLK Node = 'CLK'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.711 ns) 2.931 ns REG10B:u5\|DOUT\[7\] 2 REG LC_X16_Y16_N5 3 " "Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = LC_X16_Y16_N5; Fanout = 3; REG Node = 'REG10B:u5\|DOUT\[7\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.462 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.38 % " "Info: Total cell delay = 2.180 ns ( 74.38 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.751 ns 25.62 % " "Info: Total interconnect delay = 0.751 ns ( 25.62 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.931 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } } } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "10.260 ns" { PWORD[1] REG10B:u5|DOUT[3]~COUT0 REG10B:u5|DOUT[4]~COUT0 REG10B:u5|DOUT[5]~COUT0 REG10B:u5|DOUT[6]~COUT REG10B:u5|DOUT[7] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.931 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[2\] sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a8~porta_address_reg0 13.540 ns memory " "Info: tco from clock CLK to destination pin FOUT\[2\] through memory sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a8~porta_address_reg0 is 13.540 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.930 ns + Longest memory " "Info: + Longest clock path from clock CLK to source memory is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 449 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 449; CLK Node = 'CLK'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.722 ns) 2.930 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a8~porta_address_reg0 2 MEM M4K_X17_Y10 4 " "Info: 2: + IC(0.739 ns) + CELL(0.722 ns) = 2.930 ns; Loc. = M4K_X17_Y10; Fanout = 4; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a8~porta_address_reg0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.461 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" 299 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 74.78 % " "Info: Total cell delay = 2.191 ns ( 74.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.739 ns 25.22 % " "Info: Total interconnect delay = 0.739 ns ( 25.22 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.930 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" 299 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.960 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.960 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a8~porta_address_reg0 1 MEM M4K_X17_Y10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y10; Fanout = 4; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|ram_block3a8~porta_address_reg0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" 299 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|q_a\[2\] 2 MEM M4K_X17_Y10 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y10; Fanout = 2; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_m9t:auto_generated\|altsyncram_t5b2:altsyncram1\|q_a\[2\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.308 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[2] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/altsyncram_t5b2.tdf" 38 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.528 ns) + CELL(2.124 ns) 9.960 ns FOUT\[2\] 3 PIN PIN_164 0 " "Info: 3: + IC(3.528 ns) + CELL(2.124 ns) = 9.960 ns; Loc. = PIN_164; Fanout = 0; PIN Node = 'FOUT\[2\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "5.652 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[2] FOUT[2] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.432 ns 64.58 % " "Info: Total cell delay = 6.432 ns ( 64.58 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.528 ns 35.42 % " "Info: Total interconnect delay = 3.528 ns ( 35.42 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "9.960 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[2] FOUT[2] } "NODE_NAME" } } } } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.930 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "9.960 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[2] FOUT[2] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLK CLK_DA 5.226 ns Longest " "Info: Longest tpd from source pin CLK to destination pin CLK_DA is 5.226 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 449 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 449; CLK Node = 'CLK'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(2.124 ns) 5.226 ns CLK_DA 2 PIN PIN_167 0 " "Info: 2: + IC(1.633 ns) + CELL(2.124 ns) = 5.226 ns; Loc. = PIN_167; Fanout = 0; PIN Node = 'CLK_DA'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "3.757 ns" { CLK CLK_DA } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.593 ns 68.75 % " "Info: Total cell delay = 3.593 ns ( 68.75 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.633 ns 31.25 % " "Info: Total interconnect delay = 1.633 ns ( 31.25 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "5.226 ns" { CLK CLK_DA } "NODE_NAME" } } } } 0}
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