dds_vhdl.tan.qmsg

数字移相信号发生器设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 5 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node altera_internal_jtag~TCKUTAP is an undefined clock" {  } { { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1\|regoutff register sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened_ff\[1\] 139.96 MHz 7.145 ns Internal " "Info: Clock CLK has Internal fmax of 139.96 MHz between source register sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1\|regoutff and destination register sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened_ff\[1\] (period= 7.145 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.896 ns + Longest register register " "Info: + Longest register to register delay is 6.896 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1\|regoutff 1 REG LC_X20_Y10_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y10_N2; Fanout = 1; REG Node = 'sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1\|regoutff'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" 369 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.590 ns) 2.326 ns sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|all_bits_matched~444 2 COMB LC_X16_Y8_N9 1 " "Info: 2: + IC(1.736 ns) + CELL(0.590 ns) = 2.326 ns; Loc. = LC_X16_Y8_N9; Fanout = 1; COMB Node = 'sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|all_bits_matched~444'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.326 ns" { sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~444 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 3.344 ns sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|all_bits_matched~446 3 COMB LC_X16_Y8_N8 1 " "Info: 3: + IC(0.428 ns) + CELL(0.590 ns) = 3.344 ns; Loc. = LC_X16_Y8_N8; Fanout = 1; COMB Node = 'sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|all_bits_matched~446'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.018 ns" { sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~444 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~446 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.717 ns) + CELL(0.114 ns) 5.175 ns sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|all_bits_matched~448 4 COMB LC_X16_Y14_N0 3 " "Info: 4: + IC(1.717 ns) + CELL(0.114 ns) = 5.175 ns; Loc. = LC_X16_Y14_N0; Fanout = 3; COMB Node = 'sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|all_bits_matched~448'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.831 ns" { sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~446 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~448 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.606 ns) + CELL(0.115 ns) 6.896 ns sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened_ff\[1\] 5 REG LC_X12_Y15_N2 2 " "Info: 5: + IC(1.606 ns) + CELL(0.115 ns) = 6.896 ns; Loc. = LC_X12_Y15_N2; Fanout = 2; REG Node = 'sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened_ff\[1\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.721 ns" { sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~448 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd" 934 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.409 ns 20.43 % " "Info: Total cell delay = 1.409 ns ( 20.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.487 ns 79.57 % " "Info: Total interconnect delay = 5.487 ns ( 79.57 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "6.896 ns" { sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~444 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~446 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~448 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.012 ns - Smallest " "Info: - Smallest clock skew is 0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.931 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 449 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 449; CLK Node = 'CLK'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.711 ns) 2.931 ns sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened_ff\[1\] 2 REG LC_X12_Y15_N2 2 " "Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = LC_X12_Y15_N2; Fanout = 2; REG Node = 'sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened_ff\[1\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.462 ns" { CLK sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd" 934 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.38 % " "Info: Total cell delay = 2.180 ns ( 74.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.751 ns 25.62 % " "Info: Total interconnect delay = 0.751 ns ( 25.62 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.931 ns" { CLK sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.919 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 2.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 449 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 449; CLK Node = 'CLK'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.711 ns) 2.919 ns sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1\|regoutff 2 REG LC_X20_Y10_N2 1 " "Info: 2: + IC(0.739 ns) + CELL(0.711 ns) = 2.919 ns; Loc. = LC_X20_Y10_N2; Fanout = 1; REG Node = 'sld_signaltap:phase\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1\|regoutff'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.450 ns" { CLK sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" 369 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.68 % " "Info: Total cell delay = 2.180 ns ( 74.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.739 ns 25.32 % " "Info: Total interconnect delay = 0.739 ns ( 25.32 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.919 ns" { CLK sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.931 ns" { CLK sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.919 ns" { CLK sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd" 369 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd" 934 -1 0 } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "6.896 ns" { sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~444 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~446 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|all_bits_matched~448 sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.931 ns" { CLK sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.919 ns" { CLK sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_signaltap:phase\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|HUB_TDO~reg0 102.75 MHz 9.732 ns Internal " "Info: Clock altera_internal_jtag~TCKUTAP has Internal fmax of 102.75 MHz between source register sld_signaltap:phase\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] and destination register sld_hub:sld_hub_inst\|HUB_TDO~reg0 (period= 9.732 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.605 ns + Longest register register " "Info: + Longest register to register delay is 4.605 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:phase\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] 1 REG LC_X13_Y14_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y14_N7; Fanout = 1; REG Node = 'sld_signaltap:phase\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.272 ns) + CELL(0.590 ns) 1.862 ns sld_hub:sld_hub_inst\|HUB_TDO~818 2 COMB LC_X14_Y13_N7 1 " "Info: 2: + IC(1.272 ns) + CELL(0.590 ns) = 1.862 ns; Loc. = LC_X14_Y13_N7; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~818'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.862 ns" { sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~818 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.114 ns) 2.657 ns sld_hub:sld_hub_inst\|HUB_TDO~819 3 COMB LC_X15_Y13_N1 1 " "Info: 3: + IC(0.681 ns) + CELL(0.114 ns) = 2.657 ns; Loc. = LC_X15_Y13_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~819'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.795 ns" { sld_hub:sld_hub_inst|HUB_TDO~818 sld_hub:sld_hub_inst|HUB_TDO~819 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.292 ns) 3.676 ns sld_hub:sld_hub_inst\|HUB_TDO~820 4 COMB LC_X15_Y13_N8 1 " "Info: 4: + IC(0.727 ns) + CELL(0.292 ns) = 3.676 ns; Loc. = LC_X15_Y13_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~820'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.019 ns" { sld_hub:sld_hub_inst|HUB_TDO~819 sld_hub:sld_hub_inst|HUB_TDO~820 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.478 ns) 4.605 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 5 REG LC_X15_Y13_N3 0 " "Info: 5: + IC(0.451 ns) + CELL(0.478 ns) = 4.605 ns; Loc. = LC_X15_Y13_N3; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.929 ns" { sld_hub:sld_hub_inst|HUB_TDO~820 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.474 ns 32.01 % " "Info: Total cell delay = 1.474 ns ( 32.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.131 ns 67.99 % " "Info: Total interconnect delay = 3.131 ns ( 67.99 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.605 ns" { sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~818 sld_hub:sld_hub_inst|HUB_TDO~819 sld_hub:sld_hub_inst|HUB_TDO~820 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.937 ns + Shortest register " "Info: + Shortest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.937 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 535 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 535; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.226 ns) + CELL(0.711 ns) 4.937 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 2 REG LC_X15_Y13_N3 0 " "Info: 2: + IC(4.226 ns) + CELL(0.711 ns) = 4.937 ns; Loc. = LC_X15_Y13_N3; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.937 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.40 % " "Info: Total cell delay = 0.711 ns ( 14.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.226 ns 85.60 % " "Info: Total interconnect delay = 4.226 ns ( 85.60 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.937 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.937 ns - Longest register " "Info: - Longest clock path from clock altera_internal_jtag~TCKUTAP to source register is 4.937 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 535 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 535; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.226 ns) + CELL(0.711 ns) 4.937 ns sld_signaltap:phase\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] 2 REG LC_X13_Y14_N7 1 " "Info: 2: + IC(4.226 ns) + CELL(0.711 ns) = 4.937 ns; Loc. = LC_X13_Y14_N7; Fanout = 1; REG Node = 'sld_signaltap:phase\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.937 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.40 % " "Info: Total cell delay = 0.711 ns ( 14.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.226 ns 85.60 % " "Info: Total interconnect delay = 4.226 ns ( 85.60 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.937 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.937 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.937 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.605 ns" { sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|HUB_TDO~818 sld_hub:sld_hub_inst|HUB_TDO~819 sld_hub:sld_hub_inst|HUB_TDO~820 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.937 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.937 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } } }  } 0}