dds_vhdl.hif

数字移相信号发生器设计

q_b9
wren_a
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
e:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
e:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
e:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
e:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
e:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
e:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
e:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
e:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
altsyncram_qg82
# case_insensitive
# source_file
db|altsyncram_qg82.tdf
1134547594
6
# storage
db|dds_vhdl.(45).cnf
db|dds_vhdl.(45).cnf
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
data_a32
data_a33
data_a34
data_a35
data_a36
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
clock0
clock1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17
q_b18
q_b19
q_b20
q_b21
q_b22
q_b23
q_b24
q_b25
q_b26
q_b27
q_b28
q_b29
q_b30
q_b31
q_b32
q_b33
q_b34
q_b35
q_b36
}
# memory_file {
none
0
}
# end
# entity
sld_offload_buffer_mgr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_acquisition_buffer.vhd
1088009288
4
# storage
db|dds_vhdl.(46).cnf
db|dds_vhdl.(46).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
1
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
buffer_depth
512
PARAMETER_DEC
USR
mem_address_bits
9
PARAMETER_DEC
USR
data_bits
37
PARAMETER_DEC
USR
data_bit_cntr_bits
6
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_counter.tdf
1088009428
6
# storage
db|dds_vhdl.(47).cnf
db|dds_vhdl.(47).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
6
PARAMETER_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
37
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_iv7
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
q0
q1
q2
q3
q4
q5
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
e:|altera|quartus41|libraries|megafunctions|lpm_add_sub.inc
1081478464
e:|altera|quartus41|libraries|megafunctions|cmpconst.inc
1081478088
e:|altera|quartus41|libraries|megafunctions|lpm_compare.inc
1081478538
e:|altera|quartus41|libraries|megafunctions|lpm_counter.inc
1081478574
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|alt_synch_counter.inc
1081477038
e:|altera|quartus41|libraries|megafunctions|alt_synch_counter_f.inc
1081477054
e:|altera|quartus41|libraries|megafunctions|alt_counter_f10ke.inc
1081476700
e:|altera|quartus41|libraries|megafunctions|alt_counter_stratix.inc
1081476712
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
cntr_iv7
# case_insensitive
# source_file
db|cntr_iv7.tdf
1134547596
6
# storage
db|dds_vhdl.(48).cnf
db|dds_vhdl.(48).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_counter.tdf
1088009428
6
# storage
db|dds_vhdl.(49).cnf
db|dds_vhdl.(49).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
9
PARAMETER_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
512
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_mk7
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
e:|altera|quartus41|libraries|megafunctions|lpm_add_sub.inc
1081478464
e:|altera|quartus41|libraries|megafunctions|cmpconst.inc
1081478088
e:|altera|quartus41|libraries|megafunctions|lpm_compare.inc
1081478538
e:|altera|quartus41|libraries|megafunctions|lpm_counter.inc
1081478574
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|alt_synch_counter.inc
1081477038
e:|altera|quartus41|libraries|megafunctions|alt_synch_counter_f.inc
1081477054
e:|altera|quartus41|libraries|megafunctions|alt_counter_f10ke.inc
1081476700
e:|altera|quartus41|libraries|megafunctions|alt_counter_stratix.inc
1081476712
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
cntr_mk7
# case_insensitive
# source_file
db|cntr_mk7.tdf
1134547596
6
# storage
db|dds_vhdl.(50).cnf
db|dds_vhdl.(50).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_shiftreg.tdf
1088009432
6
# storage
db|dds_vhdl.(51).cnf
db|dds_vhdl.(51).cnf
# user_parameter {
LPM_WIDTH
37
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data1
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data2
data30
data31
data32
data33
data34
data35
data36
data3
data4
data5
data6
data7
data8
data9
enable
load
shiftin
shiftout
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_shiftreg.tdf
1088009432
6
# storage
db|dds_vhdl.(52).cnf
db|dds_vhdl.(52).cnf
# user_parameter {
LPM_WIDTH
19
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data1
data2
data3
data4
data5
data6
data7
data8
data9
enable
load
shiftin
shiftout
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
sld_rom_sr
# architecture
A:INFO_REG
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_rom_sr.vhd
1088009284
4
# storage
db|dds_vhdl.(53).cnf
db|dds_vhdl.(53).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
32
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_hub.vhd
1088009286
4
# storage
db|dds_vhdl.(54).cnf
db|dds_vhdl.(54).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
1
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone
PARAMETER_UNKNOWN
USR
n_nodes
3
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
7
PARAMETER_UNKNOWN
USR
node_info
000110000000000001101110000000000000000000011000011011100000000100000000000110000110111000000000
PARAMETER_BIN
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
}
# end
# entity
sld_jtag_state_machine
# architecture
A:rtl
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_hub.vhd
1088009286
4
# storage
db|dds_vhdl.(55).cnf
db|dds_vhdl.(55).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
1
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_shiftreg.tdf
1088009432
6
# storage
db|dds_vhdl.(56).cnf
db|dds_vhdl.(56).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
}
# include_file {